Building a Standards Converter

[ppppenguin]

The Hedghog project folder on my computer is fairly large at 12.5 MB in size.

I'd call that small for a significant project! For the VHDL just take the source files plus whatever the Altera software needs to call it a porject and zip them. You shouldn't need any of the derived files.

Definitely pipeline the oversampling multipliers. I don't know the Altera software and haven't looked at your code here but I assume that there is a facilty to generate multipliers with the right size buses and choice of pipelining. In Xilinx you can use COregen to do this, or simply infer the mutliplier with a "*". They say that if you put some extra registers before the multiplier the tools will make them into a pipeline. i've never tried this.

[`FRANK.C]

Hi Jac
The 3 line interpolater was deliberately made to give a softer picture. The difference between it and the 6 line interpolater is noticeable.

Hi Jeffrey
I will start a project and take it as far as I can without compiling. If I remember right, before compilation the project folder is well below 1 MB uncompressed.
The pin planer tool wont work without the project been compiled first. But I think I may be able to make assignments to the pins without compiling by using an assignments file.
I think it important that I make the pin assignments as any unused pins I have set to high impedance and on the PCB have connected them to GND.

I now have the oversampler multipliers pipe lined. In Quartus II the multipliers can be generated with the help of the 'MegaWizard plug-in manager' . It makes generating them very easy.

Frank

[ppppenguin]

In a FPGA unused pins are more or less floating. On a Xilinx they have a weak pull-up and Altera is probably similar. So the usual arrangement is to leave them open circuit on the PCB. No harm in connecting them to 0V. They don't need to be explicity specified. In older Xilinx software the pinouts and much else is specified in a UCF file. Here's an example pin called pSEP_MS wich is allocated to pin R24. I have also declared to be 3.3V CMOS though this could have been done globally in the design.

NET "pSEP_MS" LOC = R24 |IOSTANDARD = "LVCMOS33" ;

There must be a similar file in the Altera software.

In some very high speed designs it's recommended to ground unused pins and possibly force them to logic 0. This is to reduce ground bounce. This is definitely NOT a problem on Hedghog.

I've looked at the MegaWizard plug-in manager and it's Altera's equivalent of Xilinx Coregen.

[Jac Janssen]

Hi Jac
The 3 line interpolater was deliberately made to give a softer picture. The difference between it and the 6 line interpolater is noticeable.
Frank

Hi Frank,

Is the 3 line interpolator the same as the 2 line or 6 line, with different coefficients to get a softer picture, or does it indeed use 3 lines?
I noticed some artifacts on the 3 line and 6 line that are not present on the 2 line.
I need to experiment further with various program material (and compare to other standards converters).
(A high quality 405 line monitor would help, but non in my limited collection.)
So far I have no preference yet for one of the 3 settings. Nice to have the choice though!

Jac

[ppppenguin]

When the BBC investigated standards conversion in the 1970s they did experiments to determine how many lines to use in the interpolator. Summarising, 2 lines were essential, 3 gave signifcant improvement, 4 gave very slight improvement. More than 4 gave no visible benefit. So they used 4 lines on the CO6/509.

Since the BBC did those experiments the nature of source material has changed. Mostly it's about interframe effects, where modern cameras can have much shorter exposure times. This isn't relevant to a line converter but affects frame rate conversion. There's also a improvement to camera vertical definition though this is much smaller. Also there's much more electronically sourced material which may have rather sharp edges going down the screen. This suggests that a slightly softer aperture might be useful now when down converting. I doubt it makes much difference.

[`FRANK.C]

Hi Jeffrey
My reasoning for connecting the unused pins to GND. Was that regardless of whether they were used or not they were connected to the PCB headers and that grounding them may help reduce RFI. At least it wouldn't hurt.

Hi Jac
The 2 line interpolater uses 2 lines, the 3 line uses 3 lines and the 6 line uses 6 lines.
The 6 lines are always 'in circuit' but when doing 2 or 3 lines the unused lines are given '0' coefficients so they will have no effect.

Frank

[ppppenguin]

Indeed it won't hurt to ground them. Until you decide to do some experimental work that needs another pin. I suppose you could clip out the relevant pin(s) on the headers and solder wire(s) to the FPGA board.

[Jac Janssen]

Thanks Frank,

What I expected
The 3 and 6 line interpolation gives a same artifact as I noticed on the Aurora.
Not immediately visible on film material, but clear f.i. on the on-screen display of my cheap media player.
According to the manual 3-line interpolation is used in the Aurora. That manual further states that there is no visible difference between 3 and 4 line interpolation.

Thanks also to Frank for the latest program update.
This solved the 5:4 problem with the older program (only cropping on left hand side when using external video in).

Jac

[ppppenguin]

The Aurora does indeed use 3 line interpolation. Darryl reckoned there was no signifcant difference between 3 and 4 lines. The BBC research said the difference was minimal. I don't think 4 line was feasible in the small FPGA that Darryl uses in the Aurora.

The OSD will have sharp horizontal edges that will cause aliasing which will defeat just about any interpolator. I once had a crosshatch generator with the interlace the wrong way round. That caused havoc with interpolators.

Using line based interpolation on interlaced pictures will always be a compromise. The lines being interpolated are not spatially adjacent. But spatially adjacent lines are a field apart in time. The Pineapple converter which had field stores had a gorgeous looking interfield interpolation option. Until something moved. Then the result was unspeakbly hideous. You got similar effects with early LCD TVs where the de-interlacing was poor. De-interlacing is very hard to do well. Ultimately the vertical and temporal information are very entangled and hard to separate.

While the 1970s BBC report that I cited said there was no benefit in going above 4 lines, I've seen other work suggesting that up to 9 lines can be beneficial. I think this was only on progressive material and probably only worked if there was no vertical aliasing. Neither of these is a practical situation for a 625 to 405 converter.

[`FRANK.C]

It was because of the aliasing on the 6 line interpolater that I decided to make the interpolater switchable. As I thought that the aliasing might be intrusive but after using it for sometime now the switch never leaves the 6 line position.

Frank