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Back in November I decided to have a try at building a Standards Converter. It has been a sharp learning curve and it is only now that I have anything to show for my efforts.

I decided to go with a video decoder chip and picked the TVP5146M2 as it could be programmed to give a separate Y output at 13.5 MHz, it also has H sync , V blanking, Active video and Field ID outputs all of which are programmable. For memory I am using two AL422  FIFO's. I had initially thought that I would use two PIC's to do the control, one on the 625 side and one for 405. It then became clear that I would need some logic gates as well, as a PIC wouldn't be quick enough to do all the switching.  I have had no experience of PLD's but it seamed that this might be an application for one. To cut a long story short I decided on using a Max II EPM240T100C5 CPLD. By using the signals  from video decoder the CPLD controls and sequences the writing of the video to the FIFO's, so no PIC needed for the 625 side. A PIC18LF22K24 run from a 9 MHz crystal produces the 405 sync pulses and also programs the Video decoder
The CPLD will also do the interpolation and add the sync pulses to the video.  The output from the CPLD is fed to a R2R ladded which dose the digital to analogue conversion.

The worst part so far was trying to make a breakout board  for the video decoder as its pins are spaced 0.5 mm apart, after two failed attempts I did what I should have done in the beginning and got one made in China. There was some room left over on the board so I fitted in the FIFO's and also the R2R ladder for the DAC. The section of the board that the R2R lader was on needed to be cut apart from the rest.

A photo below of it and also one of it producing a 188 active line picture (one field repeated twice to produce a full frame) the test card is from Mike's Test Card CD.

In the weeks to come I will be putting in the other field and doing the interpolater

Frank
Well done.

I've used the AL422 many years ago in one of my professional designs. It's very easy to use to a make a simple framestore. I think the Domino converter used them too.

Not sure how you're going to do the interpolator. Does that programmable logic device contain any memory that could do a line store? I don't think it does, unlike FPGAs which usually have block RAM. For example the Aurora SCRF converters use a Xilinx Spartan 3 series device which has enough block RAM to do 3 line interpolation. If you're planning to interpolate between spatially adjacent lines on successive fields prepare to be very disappointed. It's fine on still pictures but really horrendous once things start moving. The Pineapple converter had a switch to choose interfield or intrafield interpolation. You always used it intrafield.
Hi Jeffery
My plan if it works is to use the second FIFO for interpolation storage, so I can have the discarded line stored twice
The video will be wrote to the FIFO's in such a way that when read back there would always be a kept line in one and a discarded line in the other. The sequence will be as follows, with lines B and E being the discarded lines.

FIFO A     FIFO B

line A     line B
line B     line C
line D     line E
line E     line F

and so on.


Later on I may try an optimised two line interpolater with the table of coefficients stored on the PIC, I suspect the sequence of storing the lines will need to be more complecated, but that's a long way down the road yet.

Frank
My gut feeling is that you'll run out of resources in the PLD when you try to do an interpolator. When down converting (to a lower number of lines) the simplest way to do interpolation is to have line delay(s) on the input standard. The interpolated lines are then written to the time redistribution memory. With framestores it's possible to interpolate after the time redistribution which is what I think you're trying to do.

On my own experimental converter I used ordinary SDRAM to create the appearance of a framestore with a single video write port and multiple (up to 4) video read ports. I then interpolated at the output standard. I had developed the techniques for my professional designs and had the relevant hardware available. I had written all lthis up in some detail elsewhere but unfortunately this information has been destroyed. I still have all the design files and notes but they aren't in a form that could readily be published.
Hi Jeffery
You are correct I am doing the time redistribution first then the interpolation. The two FIFO’s are read in parallel and clocked at 9 MHz, so one FIFO must be always be outputting a kept line while the other is outputting the adjacent dropped line.
My original plan before I started to use the CPLD was to feed the output of each FIFO into a DAC and do the weighting and adding of the outputs in analogue.

Doing a simple interpolater with the discarded line being split 50:50 between adjacent lines (is a linear interpolater the correct term?) should be achievable using the CPLD, anything more sophisticated is another story, but we'll see what happens.

I think I can remember reading that write up about your experimental converter, it was sometime ago.
I have read all your articles about converters on your web site, several times. They were the first thing I read when starting out and a great source of information.

Frank
Hi.
I'm watching this thread with great interest Frank.
May even see it in the flesh this year as we are heading to Ireland either September or early October. Biggrin Biggrin
The twin DAC and analogue interpolator idea was used in the Pineapple converter. I've probably got the schematic somewhere.

If you're going to use programmable logic why not go the whole hog and get a FPGA prototyping kit. I think there are some pretty inexpensive ones around. Then you've got loads of logic to play with, including block RAM (or its Altera equivalent) to make line stores. Presumably you're already programming the CPLD in VHDL or Verilog so you've overcome that hurdle.

A 50:50 interpolator is pretty simple, just an adder and a bit of multiplexing. It's vastly better than no interpolator at all but not as good as a proper 2 line interpolator.
Hi Trevor
That’s great news, I am looking forward to the Autumn already.

Hi Jeffery
I am afraid I haven’t learnt VHDL. I was going to and had downloaded a tutorial but then I discovered that the design could be entered as a schematic. For someone like myself that has no previous experience this is a quick and easy way of programming CPLD's. I will post a screen shot later. I would expect that you would have more functionality with VHDL and that it would be easier for more complex designs.

There is about 8k bit's of memory in this CPLD which should be enough for one line store if it is suitable type of memory, but as yet I don’t know what type it is, more reading to be done.

CPLD's with more resources than this one are available and as you say even FPGA's aren’t expensive. For now I will keep playing with what I have until I get the basics right and then see where to go from there.

Frank
The memory in those CPLDs is flash, not RAM. Totally unsuitable for storing lines of video.

VHDL isn't easy to learn - it's horribly confusing. I put off learning it for far too long and it was an uphill struggle. I've only learned the bits of VHDL that are useful to me, sometimes I learn a new bit when I need to. After a while you get to know how to do common constructs and it's then a LOT easier than schematic entry.

I've attached a VHDL file that's part of my experimental converter. Had to change the extension from VHD to TXT as GVR won't allow VHD files. Look, for example, at lines 164 to 195. These are the horizontal timing for the output. It's switchable from 625 to 405 so I could do all the development at 625 output where I have better testgear and also route it through a SDI output that I had available. The analogue output arrangements are in another file where, for example, just a few lines of VHDL make the mixed sync signal.

Here's a tiny bit of the file. The 13 bit central counter is trivial. HCOUNT is an integer signal which I found convenient but it could equally have been a standard logic vector.

            if HRESET then HCOUNT <= 0;                                                -- Reset at terminal count

                else            HCOUNT <= HCOUNT + 1 mod 8192;                        -- Normal count
            end if;
Hi Jeffery
Thanks for the VHDL file, I have downloaded it and when I get a chance I will study it.

I have uploaded a screen shot of part of the CPLD schematic that I am currently using. This part  controls the writing to memory. All the inputs are on the left and all except “FREEZ_FRAME” are from the video decoder. The outputs on the right go to the FIFO's. The Data clock of the video decoder is the FIFO's write clock.

Frank
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