Building a Standards Converter

[`FRANK.C]

On page 32 of the MC44BS373CA data sheet available here shows the relevant diagram. The component connected to pins 6,7 and 8 would need to be added to do FM sound. The audio then connected to where audio is indicated on the diagram.

This would need to be done to the video modulator (IC5) no need to remove anything.

Frank

[Jac Janssen]

Thanks Frank,

That certainly looks doable.
Does that mean that you can switch off the AM audio modulator (IC4) in the program?

Jac

Thanks Jeffrey for looking up how things are connected in the Aurora.

[ppppenguin]

I was wrong about intercarrier modulation. The MC44BS373CA has separate sound and vision modulators. I know that Darryl explained why System A couldn't be done with a single device but I forget the reason. I know that the combination of AM sound, +ve vision and 3.5MHz spacing wasn't possible. I'm not sure which of these 3 factors was the real problem. My guess is the 3.5MHz spacing, because the chip can do French style +ve vision with AM sound.

[`FRANK.C]

Hi Jac
Yes the modulators can be turned off individually. In Hedghog they can be turned off by means of the DIP switches.
This feature was included to aid setting up the audio carrier level.

Jeffery
You are correct it is the 3.5 MHz spacing that is the problem. The available spacings are 4.5, 5, 5.5 and 6 MHz and can be found on page 10 of the data sheet.

Frank

[ppppenguin]

Not forgetting 6.5MHz for systems L and K. The other problem was the 6dB picture to sound ratio for System A. All other systems used a rather greater ratio.

[`FRANK.C]

I updated the program so the converter can now convert from 16:9 to both 4:3 and 5:4 as well as converting from 4:3 to 4:3 and 5:4. To facilitate this the top two positions of the tone switch is now used to switch between 4:3 and 16:9 input. The selection of 400 Hz or 1KHz tone on the DIP switch SW8-D. The new program file and legends to suit can be downloaded from the Hedghog web page.

While making the changes I have been tidying up the files a little and changing them to make them a little easier to modify to do another standard. When I have them finished I will upload them here.

Frank

[ppppenguin]

Frank, would it be a good idea to put your Hedghog web page in your signature line? Then it appears automatically in every post you make. Easily done from your user panel.

[`FRANK.C]

A good piece of advice Jeffery and done.

Frank

[`FRANK.C]

I have uploaded one of the Hedghog files.
Copy the text and put it into into a VHDL file in the editor in Quartus it will look a lot better.

It's name is out_405 and most everything on the 405 side of the converter is contained in it. This is the latest version that does aspect ratio conversions of. 4:3 => 4:3, 4:3 => 5:4, 16:9 => 4:3 and 16:9 =>5:4.

There is a set of constants for each set of aspect ratios. When a aspect ratio is selected it's associated constants are loaded and used. In order to make changing standards conversion to a different standard I have included extra constants in each set.
So potentially it can do up to 4 different standards.

To do 567 lines I would suggest trying the following

Pixel clock frequency   11.19825 MHz
Full line         790 pixels =      70.55 uS
Front porch     8  pixels =      0.714 uS
Sync                 63 pixels =         5.63 uS
Back porch         17 pixels =      1.52 uS
Active line     702 pixles=         62.69 uS
Equ pulse         32 pixels =        2.86 uS
Broad pulse    330 pixels =    29.47 us

An example below of how this would fit into one set of constants. In this case selecting 16:9 => 5:4 on Hedghog would select 567 lines instead.

Code:

--------------------------------------------------------------------------------------------------
---  constants for 16:9 => 5:4 ---
-------------------------------------------------------------------------------------------------
-- changed for 567 lines
constant LINES_IN_A_FRAME_54_169 : integer := 567; -- number of lines in a frame
constant FULL_LINE_VAL_54_169 : integer := 790; -- number of pixels in a full line
constant LINE_SYNC_START_54_169 : integer := 0; -- number of pixels to start of sync
constant LINE_SYNC_STOP_54_169 : integer := 63; -- number of pixels of line sync
constant BROAD_PULSE_STOP_54_169 : integer := 330; -- number of pixels of  broad pulse
constant AVID_START_54_169 : integer := 81; -- activ video start pixel  
constant AVID_STOP_54_169 : integer := 783; -- activ video stop pixel  
constant MEM_RD_START_54_169 : integer := 71; -- memory read start pixel
constant MEM_RD_STOP_54_169 : integer := 790; -- memory read stop pixel
constant EQU_PULSE_STOP_54_169 : integer := 32; -- no of pixels of equ pulse
constant BP_START_NORM_B_54_169   : integer := 0; --broad pulse normal start 1/2 line
constant BP_STOP_NORM_B_54_169   : integer := 8; --broad pulse normal stop 1/2 line
constant BP_START_EQU_B_54_169 : integer := 6; --broad pulse with equ pulse start 1/2 line
constant BP_STOP_EQU_B_54_169 : integer := 12; --broad pulse with equ pulse stop 1/2 line
constant EQU_PULSE_START_B_54_169 : integer := 0; -- equ pulse start 1/2 line
constant EQU_PULSE_STOP_B_54_169 : integer := 18; -- equ pulse stop 1/2 line
constant AV_LINE_NO_START_54_169 : integer := 38; -- activ video start line for video output (half lines)
constant AV_LINE_NO_STOP_54_169 : integer := 561; -- activ video stop line for video output (half lines)
-- coff for oversampler clock, pixel clock =  11.19825 MHz
constant DTO_COEF_54_169 : std_logic_vector(31 downto 0) := conv_std_logic_vector(890668843, 32);

--------------------------------------------------------------------------------------------------

The 625 line file will need to be changed as well as this where the interpolation is done.
In the interpolater when the number of output lines changes. The number of coefficients per interpolated line changes as well. So a new new set of coefficients will need to be calculated for each standard.

When I get the 625 file finished I will post here.

Frank

[ppppenguin]

Frank, that set of constants looks like you've worked out how to write VHDL with good style. Remember that you can do arithmetic in those declarations. It won't sysnthesise any logic but may make it easier to write and understand. For example you wrote:
constant AVID_START_54_169 : integer := 81; -- activ video start pixel
constant AVID_STOP_54_169 : integer := 783; -- activ video stop pixel

It might be clearer to write:
constant AVID_START_54_169 : integer := 81; -- activ video start pixel
constant AVID_STOP_54_169 : integer := AVID_START_54_169 + 702; -- activ video stop pixel

That number 702 looks rather familiar