03-06-2019, 11:24 AM
I have finalised Hedghog II. I have made some small changed from the last version. The Quartus tools were whinging because I was not using a dedicated PLL output pin for the 14.31818 clock and because of that, the jitter on that clock may be increased. To be honest I think it was fine as it was but to be sure I have now used the dedicated pin.
To facilitate that I had to move the 50 MHz clock to the opposite side of the FPGA so I could use the PLL input pins on that side. With the PLL input pins that I was using the design would not fit in the FPGA. I have changed the position of the 5V reg and also slightly changed the position of the video out socket to give a little more clearance from the F connector.
When I have the files required to build it uploaded to my website. I will post a link here.
Frank
To facilitate that I had to move the 50 MHz clock to the opposite side of the FPGA so I could use the PLL input pins on that side. With the PLL input pins that I was using the design would not fit in the FPGA. I have changed the position of the 5V reg and also slightly changed the position of the video out socket to give a little more clearance from the F connector.
When I have the files required to build it uploaded to my website. I will post a link here.
Frank
