Building a Standards Converter

[ppppenguin]

I assume that the decoder chip isn't trying to "pull" the 14.318MHz xtal. It's likely that the designers of the chip chose 14.318 as a cheap and readily available xtal. The fact that it's NTSC subcarrier frequency is not important. Demodulation of PAL and NTSC signals is done with a 27MHz clock. Early work on digital decoding used subcarrier locked clocks but this gives problems when you want a line locked output. In NTSC the subcarrier isn't a multiple of H though it is a multiple of H/2 so it's not too bad. In PAL it's a multiple of H/4 with an additional 25Hz offset so much harder. In any case the digital output needs to be on a 13.5MHz clock to work with subsequent "601" processing. So it makes sense to do the decoding with a 27MHz clock.

Some decoders, such as the Techwell TW2814, go a stage further. You give the decoder a stable 27MHz clock. This menas that the chip has to have interpolation to put the luminance on an accurate orthogonal grid. It also means that the line length will vary by a few pixels depending on the input signal. I think this makes it essential to use a framestore after the decoder.

The FPGA Frank has chosen is the very smallest Cyclone IV. It's posisble that larger devices are available in the same package if Frank or anyone else wants to attempt more ambitious processing.

Frank has had the pleasure of finding just how many power rails are needed in a modern FPGA design At least it's all pretty low power in a small device like this. As things get bigger you start needing amps at 1.2V and hence switchmode regulators.