02-03-2019, 11:26 PM
Hi Jac
As Jeffrey has said Qartus will generate a type of schematic but it is far too detailed and very difficult to follow unless you are very familiar with the VHDL files.
The screen shot below is a inheritance diagram generated by Doxywizard. It might give some idea how the files are connected together.
I have listed the files below and given a brief description.
The VHLD files:
hedghog Top level entity. This is the main file. It's port connects to the outside world (the FPGA pins)
in_625 This file contains most everything that is clocked from the 625 line clock
out_405 This file contains most everything that is clocked from the 405 line clock
i2c_com This file does the I2C communications
pattern_gen This file generates the test card and greyscale.
Entity's that are created with the' MegaWizard plug-in manager':
fifo_1ld FIFOs used for a one line delay.
fifo_tr FIFO used for time redistribution
pll_1 PLL that generates a 216 MHz clock from the 27 MHz video clock. The 216 MHz clock is used to generate the over sampling and 405 clocks
pll_2 PLL that generates a 16 MHZ clock from the 50 MHz FBGA board clock. this is then used to generate the Modulators and I2C clocks.
int_mult Multipliers used in the interpolater.
output_mult Multiplier used for inserting the pedestal.
mult_os Multipliers used in the over sampler.
keep the questions coming they are all good.
Frank
As Jeffrey has said Qartus will generate a type of schematic but it is far too detailed and very difficult to follow unless you are very familiar with the VHDL files.
The screen shot below is a inheritance diagram generated by Doxywizard. It might give some idea how the files are connected together.
I have listed the files below and given a brief description.
The VHLD files:
hedghog Top level entity. This is the main file. It's port connects to the outside world (the FPGA pins)
in_625 This file contains most everything that is clocked from the 625 line clock
out_405 This file contains most everything that is clocked from the 405 line clock
i2c_com This file does the I2C communications
pattern_gen This file generates the test card and greyscale.
Entity's that are created with the' MegaWizard plug-in manager':
fifo_1ld FIFOs used for a one line delay.
fifo_tr FIFO used for time redistribution
pll_1 PLL that generates a 216 MHz clock from the 27 MHz video clock. The 216 MHz clock is used to generate the over sampling and 405 clocks
pll_2 PLL that generates a 16 MHZ clock from the 50 MHz FBGA board clock. this is then used to generate the Modulators and I2C clocks.
int_mult Multipliers used in the interpolater.
output_mult Multiplier used for inserting the pedestal.
mult_os Multipliers used in the over sampler.
keep the questions coming they are all good.
Frank
