02-03-2019, 08:33 PM
If you're working in VHDL you don't get a block diagram. I don't know about the Altera tools but the Xilinx tools will generate a sort of schematic from the VHDL. It's more or less useless as it has no understanding of the level of detail you want.
One of the arts of VHDL design is dividing up the design in a sensible way. Then you can see a hierarchy that shows the functional blocks of the design in a meaningful way. It's not easy to do a really good job here. Sometimes it may not even be possible. I usually also put a lot of comments at the start of each VHDL module, saying how it relates to those above and below it in the hierarchy. But a block diagram is nice, even if you have to sketch it out by hand.
One of the arts of VHDL design is dividing up the design in a sensible way. Then you can see a hierarchy that shows the functional blocks of the design in a meaningful way. It's not easy to do a really good job here. Sometimes it may not even be possible. I usually also put a lot of comments at the start of each VHDL module, saying how it relates to those above and below it in the hierarchy. But a block diagram is nice, even if you have to sketch it out by hand.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
