19-03-2018, 01:55 PM
Hi Jeffrey
I was using an Altera tool to build the FIR filter, it was a while ago so cant remember the details but I had to reduce the number of taps to get it to fit on the FPGA, at that time there was approximate 50% of the resources free.
I think that I may have been overambitious with the cutoff frequency
. At the time I didn't spend much time on it as it was just something that I was trying out as opposed to wanting to do it seriously.
Frank
I was using an Altera tool to build the FIR filter, it was a while ago so cant remember the details but I had to reduce the number of taps to get it to fit on the FPGA, at that time there was approximate 50% of the resources free.
I think that I may have been overambitious with the cutoff frequency
. At the time I didn't spend much time on it as it was just something that I was trying out as opposed to wanting to do it seriously.Frank
