18-03-2018, 07:31 PM
If the FPGA has plenty of mutliplier blocks then FIRs can be implemented very easily. Tighter response specification means more taps. Higher clock frequency means that each multiplier can be used for more than 1 tap. Symmetrical filters (most of the ones we're likely to need) halve the number of multipliers.
For the Xilinx tools, the automatic implementations are effciient. Just give the coefft set and a few other parameters and you get a good design. I would hope that Altera has an equivalent tool. Getting the coeffts is another matter. There are various tools using Remez Exchange (Parks-McClellan ) algorithms to optimise the coeffts. These tools tend to be expensive or very limited. Exploring the trade-offs between passband, transition band and stopband responses can be fascinating or frustrating. For example if you want a passband flatness of 1dB how many taps will it save compared to 0.5dB. I've no idea without trying it.
Frank has had to climb a very steep hill to get the results he's achieved. I'm pleased to have given him a hand on occasiona but he's done the hard work and should take the credit.
For the Xilinx tools, the automatic implementations are effciient. Just give the coefft set and a few other parameters and you get a good design. I would hope that Altera has an equivalent tool. Getting the coeffts is another matter. There are various tools using Remez Exchange (Parks-McClellan ) algorithms to optimise the coeffts. These tools tend to be expensive or very limited. Exploring the trade-offs between passband, transition band and stopband responses can be fascinating or frustrating. For example if you want a passband flatness of 1dB how many taps will it save compared to 0.5dB. I've no idea without trying it.
Frank has had to climb a very steep hill to get the results he's achieved. I'm pleased to have given him a hand on occasiona but he's done the hard work and should take the credit.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
