11-02-2018, 08:27 AM
I might well give Doxygen a try. While my own VHDL is well commented it's still useful to have a diagram of what I intended. As for getting the architecture right that's a real can of worms. You do your best at the start and find that it goes horrible as you proceed. Modules get out of hand. VHDL modules are best kept to 1000 lines or less for ease of use. Some of mine have crept nearer 1500 and rising so I need to take decsions about how to split them up. Module interfaces want to be as clean and narrow as possible which can play a large part in the structure of a design. At the opposite extreme you can end up with loads of tiny modules. Can be useful if they're re-usable in different parts of the design but otherwise a nuisance to keep in mind and a good reason to use Doxygen.
With VHDL and Verilog it's strictly speaking wrong to call the process "compiling" though most of us use term casually. The correct term is "synthesis" Ultimately it's generating hardware, not object code. Optimisation in synthesis seems to vary from fairly aggressive to ******** aggressive. Good style helps the synthesis tools to give efficient hardware. So for FPGA targets (which is what we're discussing here) that means (to give 2 examples) plenty of pipelining and avoidance of overomplex if/then/else structures. The difference between using boolean and SL for signals should make no difference at all. It almost goes without saying that you don't put gates in clock lines. Keep designs synchronous and use the CE inputs of flipflops which are easily inferred in synthesis. For a TV related design there will be stuff running once per line. So make a CE signal in the horizontal timing logic and use it as CE for the vertical logic. In this example it would be clearer if the CE was boolean (if CE then rathe than if CE='1' then) but I made the decision to keep is as SL. It's distributed down a hierachy of modules and you're not meant to use boolean types in the entity to interface to a module. It works but is deprecated. Stick to SL and SLV for module interfaces.
process (CK) begin
if rising_edge(CK) then
if CE='1' then
Loads of counters etc
end if; -- CE
end if; -- CK
end process;
Remember that type conversion (between SLV/ integer/signed etc or between boolean/bit/SL etc) is totally free. Uses no resources at all. It's purely a matter of how you describe a binary signal or group of signals. Likewise concatenation and bus splitting such as:
MYBUS <= DOG & CAT & COW & SHEEP; (the animals are all SL, MYBUS is 4 bit SLV)
HORSE <= MYBUS(2); Splitting a SL out from SLV. You can't directly split out bits from an integer. Need to convert to SLV, unsigned etc first but this is still free.
With VHDL and Verilog it's strictly speaking wrong to call the process "compiling" though most of us use term casually. The correct term is "synthesis" Ultimately it's generating hardware, not object code. Optimisation in synthesis seems to vary from fairly aggressive to ******** aggressive. Good style helps the synthesis tools to give efficient hardware. So for FPGA targets (which is what we're discussing here) that means (to give 2 examples) plenty of pipelining and avoidance of overomplex if/then/else structures. The difference between using boolean and SL for signals should make no difference at all. It almost goes without saying that you don't put gates in clock lines. Keep designs synchronous and use the CE inputs of flipflops which are easily inferred in synthesis. For a TV related design there will be stuff running once per line. So make a CE signal in the horizontal timing logic and use it as CE for the vertical logic. In this example it would be clearer if the CE was boolean (if CE then rathe than if CE='1' then) but I made the decision to keep is as SL. It's distributed down a hierachy of modules and you're not meant to use boolean types in the entity to interface to a module. It works but is deprecated. Stick to SL and SLV for module interfaces.
process (CK) begin
if rising_edge(CK) then
if CE='1' then
Loads of counters etc
end if; -- CE
end if; -- CK
end process;
Remember that type conversion (between SLV/ integer/signed etc or between boolean/bit/SL etc) is totally free. Uses no resources at all. It's purely a matter of how you describe a binary signal or group of signals. Likewise concatenation and bus splitting such as:
MYBUS <= DOG & CAT & COW & SHEEP; (the animals are all SL, MYBUS is 4 bit SLV)
HORSE <= MYBUS(2); Splitting a SL out from SLV. You can't directly split out bits from an integer. Need to convert to SLV, unsigned etc first but this is still free.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
