10-02-2018, 10:36 AM
Nick, I've looked at some comparisons between VHDL and Verilog. Verilog is definitely the simpler of the 2 languages. It has fewer types of signals, weaker typing than VHDL and a smaller range of constructs. I think it does have some better basic logic operations but nothing that can't be done in VHDL with a bit more complexity. Provided the code is intended for synthesis (as against simulation) it looks like Verilog to VHDL translation should be more or less 1 to 1 conversion, maintaining the structure of the design. VHDL to Verilog may be harder, as Verilog has no equivalent for constructs such as GENERATE which makes it easy to instantiate mutliple instances of a block of logic. Also Verilog appears not to have PACKAGES and LIBRARIES which can make it easier to re-use code across a design.
I think Verilog has extensions to increase its capabilities and some of these can go beyond what can be easily done in VHDL.
May well be a territorial thing. I think that VHDL is more common in Europe while Verilog is more widely used in the US.
I think Verilog has extensions to increase its capabilities and some of these can go beyond what can be easily done in VHDL.
May well be a territorial thing. I think that VHDL is more common in Europe while Verilog is more widely used in the US.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
