09-07-2017, 10:38 AM
Summery things have to take priority but in between I have been slowly whittling away at this project.
I had more or less decided to change to the TW9910 video decoder as it has separate Y output the same as the TVP5146 that I am currently using but the last time I looked in RS it is listed as a discontinued product. Mouser still has stock but by the time I get this project finished it will probably be discontinued there as well.
So I thought it was time to bite the bullet and follow Jeffrey's advice by converting to a 601 input. After studying the ITU-BT601 standard and Jeffrey's Video input file I managed to that and at least now I have the choice of using almost any decoder out there but I will most likely go for the TVP5150.
Apart from the Y I really only needed to extract the Field ID as all else is taken care of by counters on the FPGA but I have also execrated and used the SAV (start of active video) signal to ensure the video is centered within the 720 pixels.
I have adjusted the frequency of the output clocks to correct for I wrongly calculating for 720 pixel active line length and not as I should have 702. The new frequencies are 8.748 MHz for 4:3 giving a active line length of 80.25 uS and 8.1 MHz for 5:4 giving a active line length of 81.24 uS
I have changed the way 5:4 is produced. I was cropping the lines on the 625 side before the interpolater, this was unnecessarily complicating things. Now the 625 side remains the same for 4:3 and 5:4 mode with all 720 pixels been passed to the interpolater.
On the 405 output side when in 5:4 mode all 720 pixels are clocked out and the cropping of the lines is done by imposing blanking level in the appropriate places. This simplifies things and also has the advantage that if I ever decide to try and record on SD for example, playback can be either 4:3 or 5:4 from the same source file.
I also looked into the possibility of down sizing to a Cyclone II FPGA but found that the PLL's multipliers and deliverers had a very limited range compared to the Cyclone IV so could not achieve the output clock frequency's that I would like, so I will stick with the Cyclone IV. While browsing ebay looking at Cyclone II boards I stumbled across a different Cyclone IV development board this one has the dedicated clock pins brought out to the headers so in that regard will be much better to work with than the one I have the down side is the on board program memory chip has a much lower capacity. I have ordered one anyways to see how it will work.
Frank
I had more or less decided to change to the TW9910 video decoder as it has separate Y output the same as the TVP5146 that I am currently using but the last time I looked in RS it is listed as a discontinued product. Mouser still has stock but by the time I get this project finished it will probably be discontinued there as well.
So I thought it was time to bite the bullet and follow Jeffrey's advice by converting to a 601 input. After studying the ITU-BT601 standard and Jeffrey's Video input file I managed to that and at least now I have the choice of using almost any decoder out there but I will most likely go for the TVP5150.
Apart from the Y I really only needed to extract the Field ID as all else is taken care of by counters on the FPGA but I have also execrated and used the SAV (start of active video) signal to ensure the video is centered within the 720 pixels.
I have adjusted the frequency of the output clocks to correct for I wrongly calculating for 720 pixel active line length and not as I should have 702. The new frequencies are 8.748 MHz for 4:3 giving a active line length of 80.25 uS and 8.1 MHz for 5:4 giving a active line length of 81.24 uS
I have changed the way 5:4 is produced. I was cropping the lines on the 625 side before the interpolater, this was unnecessarily complicating things. Now the 625 side remains the same for 4:3 and 5:4 mode with all 720 pixels been passed to the interpolater.
On the 405 output side when in 5:4 mode all 720 pixels are clocked out and the cropping of the lines is done by imposing blanking level in the appropriate places. This simplifies things and also has the advantage that if I ever decide to try and record on SD for example, playback can be either 4:3 or 5:4 from the same source file.
I also looked into the possibility of down sizing to a Cyclone II FPGA but found that the PLL's multipliers and deliverers had a very limited range compared to the Cyclone IV so could not achieve the output clock frequency's that I would like, so I will stick with the Cyclone IV. While browsing ebay looking at Cyclone II boards I stumbled across a different Cyclone IV development board this one has the dedicated clock pins brought out to the headers so in that regard will be much better to work with than the one I have the down side is the on board program memory chip has a much lower capacity. I have ordered one anyways to see how it will work.
Frank
