10-05-2017, 06:50 AM
The decoder's clock requirement depends on the type of decoder. Some simply need a stable frequency, others may involve the xtal in a phaselock. For example the TVP5150 used in the SCRF uses a 14.318MHz xtal. I rather doubt that is being "pulled" in a PLL. The reason for doubting the need for phaselock is that it wouldn't be able to follow VHS replay. The decoder then produces a 27MHz clock to drive the rest of the logic that runs at input clock speed. I dimly remember using the Techwell TW2804 quadruple decoder in a design. Again dim memory suggests that it used system stable 27MHz clock and locked the video to that. I think it coped with VHS replay etcby varying the output line length. I think that was coped with by subsequent memory in the overall design.
If you can guarantee presence of clock from anywhere such as a decoder at startup time then use it by all means. Otherwise you've sawn off yopur own branch.
If you're using linestore then you must derive the 405 clock from the decoder's 27MHz output. With framestores you're free to choose to do that or have a separate clock.
Typically a decoder will drive a FPGA or other LSI chip and nothing else. Via short-ish tracks. The capacitative loading is usually fairly non-critical. The values on the data sheet are just those used for test conditions.
If you can guarantee presence of clock from anywhere such as a decoder at startup time then use it by all means. Otherwise you've sawn off yopur own branch.
If you're using linestore then you must derive the 405 clock from the decoder's 27MHz output. With framestores you're free to choose to do that or have a separate clock.
Typically a decoder will drive a FPGA or other LSI chip and nothing else. Via short-ish tracks. The capacitative loading is usually fairly non-critical. The values on the data sheet are just those used for test conditions.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
