09-05-2017, 10:36 PM
Thanks Jeffrey and Trevor.
I think I was asking too much from the video decoder as well. I cant find any figures for the TVP5146 but similar decoders I have seen have a maximum output load capacitance per pin of around 15pF. The data output of the decoder was driving both FIFO's which each had input capacitance of 7pF. This together with the track capacitance would easily take it over 15pF. Worse again was the data clock which was driving the FIFO's and the FPGA.
I was looking at the Intersil TW9910 decoder and the crystal/clock that it requires is 27MHz.
I was thinking that if I was to use this decoder that I could replace the 50MHz clock on the FPGA with a 27MHz one and drive the Decoders clock input from the FPGA. I could run the PLL from this 27MHz clock to produce the 405 clocks and it would also remove the need for a start up oscillator that I have at present.
BUT this would only work if the 27MHz data clock that the decoder produces is the exact same frequency as the Decoders 27MHz crystal/clock.
I suspect that the data clock would have to be locked to incoming video signal and drift with it, so therefore would be slightly different to the clock frequency. If that is the case it wont work as the 405 clocks would not be locked to the data clock which they need to be.
Frank
I think I was asking too much from the video decoder as well. I cant find any figures for the TVP5146 but similar decoders I have seen have a maximum output load capacitance per pin of around 15pF. The data output of the decoder was driving both FIFO's which each had input capacitance of 7pF. This together with the track capacitance would easily take it over 15pF. Worse again was the data clock which was driving the FIFO's and the FPGA.
I was looking at the Intersil TW9910 decoder and the crystal/clock that it requires is 27MHz.
I was thinking that if I was to use this decoder that I could replace the 50MHz clock on the FPGA with a 27MHz one and drive the Decoders clock input from the FPGA. I could run the PLL from this 27MHz clock to produce the 405 clocks and it would also remove the need for a start up oscillator that I have at present.
BUT this would only work if the 27MHz data clock that the decoder produces is the exact same frequency as the Decoders 27MHz crystal/clock.
I suspect that the data clock would have to be locked to incoming video signal and drift with it, so therefore would be slightly different to the clock frequency. If that is the case it wont work as the 405 clocks would not be locked to the data clock which they need to be.
Frank
