17-04-2017, 10:13 AM
I decided to tackle the 5:4 output next. I use the Active video signal from the video decoder to operate the write enable of the FIFO's. For 4:3 it is high for 720 pixels duration. The start and stop of the Active video signal can be programed pixel by pixel, by the I2c bus. For 5:4 output the start is moved later by 22 pixels and the stop moved earlier by 23 pixels giving a active line length of 675 pixels.
As the video decoder would be programed each time the aspect ratio was changed now seemed a good time to move the I2c master from the microcontroller to the FPGA. The microcontroller would then be redundant as this is the only function it is doing.
I cobbled together a bit banger for the FPGA but there was no activity at all from it, after a bit of head scratching I found the reason. The only clock source I have is the 27/ 13.5 MHz from the Video decoder but inconveniently at start up, by default there is no clock output, it has to be switched on by the I2c bus. So for now I have left in place the microcontroller to provide a clock for I2c master.
The first photo is of the 4:3 output and the second is of 5:4 output without changing any controls on the TV.
Frank
As the video decoder would be programed each time the aspect ratio was changed now seemed a good time to move the I2c master from the microcontroller to the FPGA. The microcontroller would then be redundant as this is the only function it is doing.
I cobbled together a bit banger for the FPGA but there was no activity at all from it, after a bit of head scratching I found the reason. The only clock source I have is the 27/ 13.5 MHz from the Video decoder but inconveniently at start up, by default there is no clock output, it has to be switched on by the I2c bus. So for now I have left in place the microcontroller to provide a clock for I2c master.
The first photo is of the 4:3 output and the second is of 5:4 output without changing any controls on the TV.
Frank
