Hi Jeffrey
I hooked up the PLL to a IO pin which gave a error message, I then looked up the instructions
.
They claim that by using only the dedicated clock pins it keeps jitter to a minimum. The only other thing that the PLL can be driven from is another PLL.
I tried googling it as well but I couldn't find anything hat helped.
I guess every chip family has it's quirks.
If there was just one of the seven clock pins on the header it would have helped a lot. There is another development board for the EP4CE10F17C8N FPGA and it don't appear to have any clock pins on it's headers either.
Frank
I hooked up the PLL to a IO pin which gave a error message, I then looked up the instructions
. They claim that by using only the dedicated clock pins it keeps jitter to a minimum. The only other thing that the PLL can be driven from is another PLL.
I tried googling it as well but I couldn't find anything hat helped.
I guess every chip family has it's quirks.
If there was just one of the seven clock pins on the header it would have helped a lot. There is another development board for the EP4CE10F17C8N FPGA and it don't appear to have any clock pins on it's headers either.
Frank
