07-04-2017, 02:07 PM
Just an update of progress.
I have move the 405 sync generation from the microcontroller to the FPGA. I also noticed that the write sequence wasn't resetting correctly and have corrected that.
For 405 4:3 out I have chosen a frequency of 8.91 MHz which gives 880 pixels per full line. It will sync with 625 and the PLL can produce it from a 13.5 MHz clock.
One fly in the ointment is the PLL's in the FPGA will only work from a dedicated clock pin and no clock pin is available on the headers on the development board. The only way around this was to remove the 50 MHz oscillator on the board and use it's pad that connects to the clock pin, which I have done and I am now getting the 8.91 MHz 405 clock from the PLL. When I first tried it the output was very poor, very jittery with line tearing. The 13.5 MHz clock from the video decoder was getting corrupted, probably through the wire that I have used to connect it to the pad. Placing a 10 pf cap between it and ground has cured it though.
I have used the two FF method the Jeffrey described to sync the 405 to 625 and it works well. There was no need to do that but it was good to try in case I need it in the future.
Ive been working out what clock to use for 5:4 video. With 720 pixels been used for 4:3 I reckon that 675 pixels would be right for 5:4. 720/1.33*1.25=675.
8.353125 MHz works out well. The PLL can produce it simultaneously with the 8.91 MHz clock and it will sync with 625. The active line length is 80.81 uS which is the same as 720 pixels at 8.91 MHz.
There is an uneven number of pixels in a full line so it will need to be clocked at twice pixel frequency in order to produce the half lines, which is not a problem as the PLL can do that.
Progress will be slow and sporadic over the summer months but I will update as things progress.
Frank
I have move the 405 sync generation from the microcontroller to the FPGA. I also noticed that the write sequence wasn't resetting correctly and have corrected that.
For 405 4:3 out I have chosen a frequency of 8.91 MHz which gives 880 pixels per full line. It will sync with 625 and the PLL can produce it from a 13.5 MHz clock.
One fly in the ointment is the PLL's in the FPGA will only work from a dedicated clock pin and no clock pin is available on the headers on the development board. The only way around this was to remove the 50 MHz oscillator on the board and use it's pad that connects to the clock pin, which I have done and I am now getting the 8.91 MHz 405 clock from the PLL. When I first tried it the output was very poor, very jittery with line tearing. The 13.5 MHz clock from the video decoder was getting corrupted, probably through the wire that I have used to connect it to the pad. Placing a 10 pf cap between it and ground has cured it though.
I have used the two FF method the Jeffrey described to sync the 405 to 625 and it works well. There was no need to do that but it was good to try in case I need it in the future.
Ive been working out what clock to use for 5:4 video. With 720 pixels been used for 4:3 I reckon that 675 pixels would be right for 5:4. 720/1.33*1.25=675.
8.353125 MHz works out well. The PLL can produce it simultaneously with the 8.91 MHz clock and it will sync with 625. The active line length is 80.81 uS which is the same as 720 pixels at 8.91 MHz.
There is an uneven number of pixels in a full line so it will need to be clocked at twice pixel frequency in order to produce the half lines, which is not a problem as the PLL can do that.
Progress will be slow and sporadic over the summer months but I will update as things progress.
Frank
