21-03-2017, 08:37 PM
(This post was last modified: 21-03-2017, 08:38 PM by ppppenguin.)
My experience of decoder chips is that they give 27MHz out. Not yet seen one that gives 13.5MHz but happy to be proven wrong. You could program the decoder from the FPGA. It's not too hard to write a "bit banger" that will do the job.
If there's a framestore in the system the input and output clocks can be completely independent of each other. If you are using linestores then they must be related.
Generating TV syncs in an FPGA is easy enough. Divide down from clock to half lines and a further divide by 2 for full lines. Once every half line you enable the field counter. The odd/even field falls out naturally from all this. The pulses are generated with JK flipflops. It's all there in the video_output file. It may look a bit more complicated because I have used some named constants. For me that made it simpler, especially if I was tweaking the timings. Meant all pulses moved in step with the offset. You can of course play with variable width pulses if you have some way of controlling the FPGA from an external microcontroller or PC. You'll see a load of that, effectively memory mapped "write only" registers, going on in the section that starts:
process (CKC) begin
if rising_edge(CKC) then
CKC is the control system clock. Can't remember what it was, probably same as one of the video clocks. In another VHDL module there's the interface between an x51 class CPU and my internal control buses. I've used this approach with minor variations for as long as I can remember.
I've occasionally wondered about doing a VHF modualtor in an FPGA. Nice to see you've tried it and made it work.
If there's a framestore in the system the input and output clocks can be completely independent of each other. If you are using linestores then they must be related.
Generating TV syncs in an FPGA is easy enough. Divide down from clock to half lines and a further divide by 2 for full lines. Once every half line you enable the field counter. The odd/even field falls out naturally from all this. The pulses are generated with JK flipflops. It's all there in the video_output file. It may look a bit more complicated because I have used some named constants. For me that made it simpler, especially if I was tweaking the timings. Meant all pulses moved in step with the offset. You can of course play with variable width pulses if you have some way of controlling the FPGA from an external microcontroller or PC. You'll see a load of that, effectively memory mapped "write only" registers, going on in the section that starts:
process (CKC) begin
if rising_edge(CKC) then
CKC is the control system clock. Can't remember what it was, probably same as one of the video clocks. In another VHDL module there's the interface between an x51 class CPU and my internal control buses. I've used this approach with minor variations for as long as I can remember.
I've occasionally wondered about doing a VHF modualtor in an FPGA. Nice to see you've tried it and made it work.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
