21-03-2017, 08:05 PM
Hi Jeffrey
You are quite correct, yesterday I had another play with the PLL to see what it could do, and pushed the output frequency up to 450Mhz where it worked quite happily. The DTO was adjusted accordingly to give the 9 MHz output. I have just lookup the speed grade of the device I have and it is 402 MHz oops!
I also found that the PLL could produce a 9 MHz clock itself , but then I wouldn’t have learnt anything about DTO's.
It would seem that the sensible thing to do is to clock the PLL from the 13.5 MHz write clock and get the PLL to produce 9 MHz from that, as at some stage I will probably try and use the FPGA's internal memory and to do that the 625 and 405 clocks would need to be synced.
Before I can do that I will need to move the sync generation and read control from the microcontroller to the FPGA. This is because the video decoder, where the 13.5 MHz is sourced from starts up with a 27 MHz clock and it is only after the microcontroller programs it that it produces 13.5 MHz. The problem with this is at start up the microcontroller would be clocked at 18 MHz. In its current set up it cant cope with that high of frequency and therefore would not be able to program the video decoder.
Generating sync in the FPGA is a totally different ball game to doing it with a microcontroller, its something I will have to spend some time thinking about to get my head around. I have browsed your video_output file, it is very well documented and has given me some ideas. As I will try to do a 5:4 output as well an 4:3, I will need to keep that in mind while doing the syncs. I will also need to figure out how well the 5:4 clock will sync up with the 625 if using the internal memory.
While using the PLL at 450 MHz I decided to see would it be possible to get modulated RF out instead of Video. I pulsed the outputs to the DAC R2R ladder with a 51.75 MHz clock ( channel 2), by 'AND' ing the outputs with a 51.75 MHz clock. The results are shown below. This is just over air with no lead used. The last photo and best results were obtained by leaving a finger on the appropriate place on the R2R ladder. It might be worth pursuing at some stage.
Frank
You are quite correct, yesterday I had another play with the PLL to see what it could do, and pushed the output frequency up to 450Mhz where it worked quite happily. The DTO was adjusted accordingly to give the 9 MHz output. I have just lookup the speed grade of the device I have and it is 402 MHz oops!
I also found that the PLL could produce a 9 MHz clock itself , but then I wouldn’t have learnt anything about DTO's.
It would seem that the sensible thing to do is to clock the PLL from the 13.5 MHz write clock and get the PLL to produce 9 MHz from that, as at some stage I will probably try and use the FPGA's internal memory and to do that the 625 and 405 clocks would need to be synced.
Before I can do that I will need to move the sync generation and read control from the microcontroller to the FPGA. This is because the video decoder, where the 13.5 MHz is sourced from starts up with a 27 MHz clock and it is only after the microcontroller programs it that it produces 13.5 MHz. The problem with this is at start up the microcontroller would be clocked at 18 MHz. In its current set up it cant cope with that high of frequency and therefore would not be able to program the video decoder.
Generating sync in the FPGA is a totally different ball game to doing it with a microcontroller, its something I will have to spend some time thinking about to get my head around. I have browsed your video_output file, it is very well documented and has given me some ideas. As I will try to do a 5:4 output as well an 4:3, I will need to keep that in mind while doing the syncs. I will also need to figure out how well the 5:4 clock will sync up with the 625 if using the internal memory.
While using the PLL at 450 MHz I decided to see would it be possible to get modulated RF out instead of Video. I pulsed the outputs to the DAC R2R ladder with a 51.75 MHz clock ( channel 2), by 'AND' ing the outputs with a 51.75 MHz clock. The results are shown below. This is just over air with no lead used. The last photo and best results were obtained by leaving a finger on the appropriate place on the R2R ladder. It might be worth pursuing at some stage.
Frank
