Building a Standards Converter

[ppppenguin]

In VHDL there are several ways of describing an array of bits. The most basic is std_logic_vector. UNSIGNED and SIGNED (2's complement) are different ways of looking at an SLV and can be better when doing arithmetic. INTEGER is still the same array of bits but is a little more complicated. I won't attempt to describe them since there's a rather useful document I found and attached.

I'm a bit old fashioned in my library delcarations and use:

library IEEE;

use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;

There are more modern ways but these can subtly affect the way arithmetic is done and how you cast between the various ways of describing an array of bits. The attached document is very useful on this.

Incidentally NEVER declare:
use IEEE.std_logic_SIGNED.ALL;

It will land you in trouble. You are free to use SIGNED signals regardless.

When doing a multiplier as a video fader it can be useful to have the video as a SIGNED signal (allowing the video to have -ve values, ie go below black) but the control signal is strictly +ve and so is declared UNSIGNED. Can equally use INTEGERS, which can be declared as +ve only or 2's complement.