15-03-2017, 03:01 PM
This file could be a bit confusing because it has lots of stuff to do with SDRAM access which is very specific to my board.
Lines 689 -699 are of special interest. This is where I use a DTO to control the vertical size and/or conversion ratio. Iuses a clock enable at H rate (HRESET) so the DTO is incremented once per TV line. The actual addtion is on line 697 where I add SDRAM_VERT_INCREMENT (set in a register previously) to the accumulated value. On line 222 I note that 128 gives no change while 195 is about right for 405 conversion.
For ease of development I made the output of my converter switchable from 405 to 625. Hence I could get most of it working on 625 where I have better testgear. Notably I have the luxury of a serial digital (SDI) output on 625 so I can use the analysis tools I have for this standard. It's fun to adjust SDRAM_VERT_INCREMENT and watch the 625 picture height being expanded or shrunk.
The fractional part of SDRAM_READ_VCOUNT (to the right of the binary point if you wish to look at it that way) drives the interpolator. That fractional part tells you how an output line is placed between inputs lines. A value of 0 means coincident, 1000000 (it's a 7 bit value in my design) means halfway down while 1111111 means almost at the next line. For a 2 line interpolator this can drive the multiplier directly. For 3 or 4 lines it needs an interoplation aperture programmed into a lookup table. I've done some experiments but not come to a conclusion. Choosing the aperture needs care. At one extreme you can reduce vertical resolution too much. At the other extreme (with -ve coeffts for some of the lines) it looks nasty and edgy.
Since the XC2S200 device doesn't have any hardware multipliers I used the Xilinx Coregen tool to build one. I was keen to keep down the size in a small device. In theory I could have just written the mutliplication inline, letting the synthesis tools build one for me. But this would have given a poor result in this device, slow due to lack of pipelining and quite possibly big due to poor optimisation.
The multiplier is instantiated at line 613. I'd planned this design to be expandable to 405 line NTSC hence the note on line 612 about C (Chroma). Because I'm running the 405 section clock at 4x pixel speed, that single multiplier can do all 4 multiplies for a 4 line aperture. (Lines 622-633 are the interpolator)
There's plenty of scope for getting things wrong in a design like this. I made lots of mistakes, which you won't see here. Thank goodness for FPGAs where you can put them right with ease.
Frank, I realise I've thrown a lot of complicated stuff at you to read and digest. If you have any question please feel free to ask.
Lines 689 -699 are of special interest. This is where I use a DTO to control the vertical size and/or conversion ratio. Iuses a clock enable at H rate (HRESET) so the DTO is incremented once per TV line. The actual addtion is on line 697 where I add SDRAM_VERT_INCREMENT (set in a register previously) to the accumulated value. On line 222 I note that 128 gives no change while 195 is about right for 405 conversion.
For ease of development I made the output of my converter switchable from 405 to 625. Hence I could get most of it working on 625 where I have better testgear. Notably I have the luxury of a serial digital (SDI) output on 625 so I can use the analysis tools I have for this standard. It's fun to adjust SDRAM_VERT_INCREMENT and watch the 625 picture height being expanded or shrunk.
The fractional part of SDRAM_READ_VCOUNT (to the right of the binary point if you wish to look at it that way) drives the interpolator. That fractional part tells you how an output line is placed between inputs lines. A value of 0 means coincident, 1000000 (it's a 7 bit value in my design) means halfway down while 1111111 means almost at the next line. For a 2 line interpolator this can drive the multiplier directly. For 3 or 4 lines it needs an interoplation aperture programmed into a lookup table. I've done some experiments but not come to a conclusion. Choosing the aperture needs care. At one extreme you can reduce vertical resolution too much. At the other extreme (with -ve coeffts for some of the lines) it looks nasty and edgy.
Since the XC2S200 device doesn't have any hardware multipliers I used the Xilinx Coregen tool to build one. I was keen to keep down the size in a small device. In theory I could have just written the mutliplication inline, letting the synthesis tools build one for me. But this would have given a poor result in this device, slow due to lack of pipelining and quite possibly big due to poor optimisation.
The multiplier is instantiated at line 613. I'd planned this design to be expandable to 405 line NTSC hence the note on line 612 about C (Chroma). Because I'm running the 405 section clock at 4x pixel speed, that single multiplier can do all 4 multiplies for a 4 line aperture. (Lines 622-633 are the interpolator)
There's plenty of scope for getting things wrong in a design like this. I made lots of mistakes, which you won't see here. Thank goodness for FPGAs where you can put them right with ease.
Frank, I realise I've thrown a lot of complicated stuff at you to read and digest. If you have any question please feel free to ask.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
