13-03-2017, 11:02 PM
Glad to hear you're getting on OK with VHDL. I'll try to add a few handy hints over the following days. These should include:
Use of clock enables
Correct use of conditional statements (IF, WHEN, WITH and CASE)
Avoiding transparent latches
Libraries and arithmetic.
In many cases you hardly need to know about the physical structure of the device. Just let the tools translate your logical thoughts from VHDL to hardware. Of course if you're going for high performance or short of space then you have more need to know.
Use of clock enables
Correct use of conditional statements (IF, WHEN, WITH and CASE)
Avoiding transparent latches
Libraries and arithmetic.
In many cases you hardly need to know about the physical structure of the device. Just let the tools translate your logical thoughts from VHDL to hardware. Of course if you're going for high performance or short of space then you have more need to know.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
