24-02-2017, 07:32 AM
Look carefully at the flipflops you are using. You may find that some have synchronous set and reset inputs while others are async. Avoid the async ones unless you know exactly what you want to achieve.
The great thing about synchronous logic is that it"just works" provided hat you don't exceed the maximum clock speed as predicted by the CPLD/FPGA tools for your designs. At the clock speeds you'll be using you'd have to try very hard to run into that sort of problem.
The great thing about synchronous logic is that it"just works" provided hat you don't exceed the maximum clock speed as predicted by the CPLD/FPGA tools for your designs. At the clock speeds you'll be using you'd have to try very hard to run into that sort of problem.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
