22-02-2017, 02:53 PM
The memory in those CPLDs is flash, not RAM. Totally unsuitable for storing lines of video.
VHDL isn't easy to learn - it's horribly confusing. I put off learning it for far too long and it was an uphill struggle. I've only learned the bits of VHDL that are useful to me, sometimes I learn a new bit when I need to. After a while you get to know how to do common constructs and it's then a LOT easier than schematic entry.
I've attached a VHDL file that's part of my experimental converter. Had to change the extension from VHD to TXT as GVR won't allow VHD files. Look, for example, at lines 164 to 195. These are the horizontal timing for the output. It's switchable from 625 to 405 so I could do all the development at 625 output where I have better testgear and also route it through a SDI output that I had available. The analogue output arrangements are in another file where, for example, just a few lines of VHDL make the mixed sync signal.
Here's a tiny bit of the file. The 13 bit central counter is trivial. HCOUNT is an integer signal which I found convenient but it could equally have been a standard logic vector.
if HRESET then HCOUNT <= 0; -- Reset at terminal count
else HCOUNT <= HCOUNT + 1 mod 8192; -- Normal count
end if;
VHDL isn't easy to learn - it's horribly confusing. I put off learning it for far too long and it was an uphill struggle. I've only learned the bits of VHDL that are useful to me, sometimes I learn a new bit when I need to. After a while you get to know how to do common constructs and it's then a LOT easier than schematic entry.
I've attached a VHDL file that's part of my experimental converter. Had to change the extension from VHD to TXT as GVR won't allow VHD files. Look, for example, at lines 164 to 195. These are the horizontal timing for the output. It's switchable from 625 to 405 so I could do all the development at 625 output where I have better testgear and also route it through a SDI output that I had available. The analogue output arrangements are in another file where, for example, just a few lines of VHDL make the mixed sync signal.
Here's a tiny bit of the file. The 13 bit central counter is trivial. HCOUNT is an integer signal which I found convenient but it could equally have been a standard logic vector.
if HRESET then HCOUNT <= 0; -- Reset at terminal count
else HCOUNT <= HCOUNT + 1 mod 8192; -- Normal count
end if;
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
