21-02-2017, 07:14 PM
Hi Jeffery
You are correct I am doing the time redistribution first then the interpolation. The two FIFO’s are read in parallel and clocked at 9 MHz, so one FIFO must be always be outputting a kept line while the other is outputting the adjacent dropped line.
My original plan before I started to use the CPLD was to feed the output of each FIFO into a DAC and do the weighting and adding of the outputs in analogue.
Doing a simple interpolater with the discarded line being split 50:50 between adjacent lines (is a linear interpolater the correct term?) should be achievable using the CPLD, anything more sophisticated is another story, but we'll see what happens.
I think I can remember reading that write up about your experimental converter, it was sometime ago.
I have read all your articles about converters on your web site, several times. They were the first thing I read when starting out and a great source of information.
Frank
You are correct I am doing the time redistribution first then the interpolation. The two FIFO’s are read in parallel and clocked at 9 MHz, so one FIFO must be always be outputting a kept line while the other is outputting the adjacent dropped line.
My original plan before I started to use the CPLD was to feed the output of each FIFO into a DAC and do the weighting and adding of the outputs in analogue.
Doing a simple interpolater with the discarded line being split 50:50 between adjacent lines (is a linear interpolater the correct term?) should be achievable using the CPLD, anything more sophisticated is another story, but we'll see what happens.
I think I can remember reading that write up about your experimental converter, it was sometime ago.
I have read all your articles about converters on your web site, several times. They were the first thing I read when starting out and a great source of information.
Frank
