30-07-2015, 03:56 PM
Thanks once more for the helpful advice guys.
I've modified the layout and the track-side mask accordingly, as follows:
1) D3 moved to the right, away from the MOS-FET - the left-hand end of D3 aligned as suggested, with the left-hand pad for SK2 to increase the space available for a heat sink if required.
2) C3 repositioned - now adjacent to IC2 output, and its value changed from 100nF to 330nF.
3) C5 repositioned to be adjacent to IC2 input.
Amended layouts of component side and track side are attached.
Hope that covers all aspects!
I've modified the layout and the track-side mask accordingly, as follows:
1) D3 moved to the right, away from the MOS-FET - the left-hand end of D3 aligned as suggested, with the left-hand pad for SK2 to increase the space available for a heat sink if required.
2) C3 repositioned - now adjacent to IC2 output, and its value changed from 100nF to 330nF.
3) C5 repositioned to be adjacent to IC2 input.
Amended layouts of component side and track side are attached.
Hope that covers all aspects!
Regards, David.
BVWS Member.
G-QRP Club Member 1339.
'I'm in my own little world, but I'm happy, and they know me here'
BVWS Member.
G-QRP Club Member 1339.
'I'm in my own little world, but I'm happy, and they know me here'







