Building a Standards Converter

[Semir_DE]

Still need a modulator. Don't know how wideband the devices in the Hedghog and Aurora are.

Hi Jeffrey,

I am currently making a modulator which is admittedly very old school using an SA612 as a vision and sound AM modulator. Since obtaining crystals with the right frequency is a hassle I have decided to build a simple PLL circuit using old Motorola MC145106 (for Band I) or MC145151 (for Band III) PLL chips. My intention is to design something that works with generally available parts and does not require programming skills, software or adapters. The reference is a simple 4MHz crystal.  The design will consist of the following building blocks:

- MC145106/MC145151 PLL chip for vision carrier
- MB501 Prescaler /64 for vision part
- SA612 AM modulator for vision positive modulation

- MC145106/MC145151 PLL chip for sound carrier
- MB501 Prescaler /64 for sound part
- SA612 AM modulator for audio AM modulation

Alternatively I am going to try the TDA5660 for systems with FM sound, here only a single PLL system is needed.

All the parts needed can be obtained from China for a few pennies each. When everything is up and running I will make a PCB board for the modulators. The vision PLL and modulator for Band I is already working very nicely and I can precisely tune to any of the 5 Band I System A channels with a DIP switch. Later I will include a 6 position rotary switch for channel selection. The design will also incorporate a 5th order output LPF in order to eliminate harmonics.

Semir

[`FRANK.C]

Hedghog II

Hedghog II is mainly in response to all the recent trouble with the EP2C5 FPGA boards. For the most part it is the Same as Hedghog but with a few changes.

What's new in Hedghog II?
The biggest difference is the FPGA board is dispensed with. Now all the components are mounted on a single PCB.
The FPGA is changed to a more modern EP4CE6E22C8N.
The R2R DAC is changed from 9 bit to 10 bit.
It now can be used in modulator only mode.
The video out socked is moved to the rear panel and an extra toggle switch is added to the front panel.
The DIP switch is now a 6 pole type.
It has a test mode that drives the Test card from the 50 MHz clock. This will allow the 405 side of the FPGA to be tested without the video clock been required and so should help to identify video decoder problems.

There are some circuit changes.
A 50 MHz oscillator feeds the FPGA. From this the FPGA then generates all the other clocks. This includes a 14.31818 MHz clock for the video decoder which previously required it's own 14.31818 MHz crystal.
The pull-up resistors for the switches have been removed and it now uses the weak pull-up's provided by the FPGA.
The unused section of the video amplifier chip is now used together with a  analogue switch to enable it to be used in modulator only mode.
To provide all the required power rails there are now 5 voltage regulators 5V, 3.3V, 2.5V, 1.8V and 1.2V.
It still fits on a double sided PCB of the same dimensions as the Hedghog PCB and so will fit the same cases.

Even though the EP4CE6E is a more modern FPGA with more resources on it that the EP2C5, it cost less.
The FPGA flash memory recommended for use with the EP4CE6E is the EPCS16SI8N. I have used the IS25LP016D-JNLE-TR which is pin for pin compatible and is a fraction of the cost.

The FPGA might look intermediating to solder but the pin pitch is the same as the video decoder. So if you are able to solder the video decoder there is no reason why you cant solder the FPGA, it just takes a little longer. In fact the I find FPGA easier to  position because it is larger and because of it's size it is easy to place tape across it to hold it in place while soldering it.
On the underside of the FPGA there is a pad which must be connected to ground. A hole has been left in the PCB underneath the FPGA to facilitate this.

It is not complete yet I just got the board finished tonight. I have some test to do on it and some files to write and tidy up.

Frank

[ppppenguin]

Frnak, you've been busy!

I hope the decoder is happy with derived 14.318MHz clock. Presumably using a DTO so it won't have equal length cycles. I don't think I'd have dared do this.

[Jac Janssen]

Again, very impressive Frank!

Jac

[ppppenguin]

I assume that the decoder chip isn't trying to "pull" the 14.318MHz xtal. It's likely that the designers of the chip chose 14.318 as a cheap and readily available xtal. The fact that it's NTSC subcarrier frequency is not important. Demodulation of PAL and NTSC signals is done with a 27MHz clock. Early work on digital decoding used subcarrier locked clocks but this gives problems when you want a line locked output. In NTSC the subcarrier isn't a multiple of H though it is a multiple of H/2 so it's not too bad. In PAL it's a multiple of H/4 with an additional 25Hz offset so much harder. In any case the digital output needs to be on a 13.5MHz clock to work with subsequent "601" processing. So it makes sense to do the decoding with a 27MHz clock.

Some decoders, such as the Techwell TW2814, go a stage further. You give the decoder a stable 27MHz clock. This menas that the chip has to have interpolation to put the luminance on an accurate orthogonal grid. It also means that the line length will vary by a few pixels depending on the input signal. I think this makes it essential to use a framestore after the decoder.

The FPGA Frank has chosen is the very smallest Cyclone IV. It's posisble that larger devices are available in the same package if Frank or anyone else wants to attempt more ambitious processing.

Frank has had the pleasure of finding just how many power rails are needed in a modern FPGA design At least it's all pretty low power in a small device like this. As things get bigger you start needing amps at 1.2V and hence switchmode regulators.

[Terry]

Something which you will have noticed when you mounted the components, but I'm fascinated to note the way that the legend for C47 is uniquely (unless I've missed any others) is printed upside down but with the characters in the correct order!

[ppppenguin]

Looks like the PCB layout software thought that legend should have been on the other side of the PCB for some reason. Very odd.

I haven't looked at programming Altera devices in detail but you've used a commonplace SPI memory this time. Hence the low cost. I don't know if Cyclone II can be programmed from standard SPI devices. I also note a JTAG port on the PCB. Cyclcone IV FPGAs can be programmed from JTAG but not sure if the SPI can be programmed via JTAG and the FPGA.

[`FRANK.C]

Terry
C47 is my bad. In the PCB software to move a component from the top side of the PCB to the bottom or visa versa you "Flip" it. You can use the same command on text which gives a mirror image of the text without changing which side of the PCB it is on. Looks like I inadvertently flipped "C47"
This PCB went wrong in a few ways. There is no silk screen on the bottom of the board.
I did a design rule check on the PCB which reported everything OK and shortly afterwards generated the Gerber files. In that short time two via's got moved close to a near by track and caused a short. I wouldn't mind but I took my time with it if I didn't it probably would have went better.
None of the problems are major. To remove the short on the track just requires running a scalpel blade beside it. I had discovered the short before the PCB arrived.

Jeffrey
The PLL's in the Cyclone IV are more capable than the ones in Cyclone II. There are two in the EP4CE6E. One uses the 27 MHz video clock to produce the 625 and 405 clocks as in Hedghog.
The other uses the 50 MHz clock and produces 14.31818 for the video decoder, 4 MHz for the modulators and a 210 MHz clock that I can run the test card off when in test mode.

To program the Flash I use indirect programming, so it gets programmed via the FPGA using a .jic file. That is the same way I program the FPGA board in Hedghog.
The Altera programmer recognises a IS25LP016D-JNLE-TR  as if it were a EPCS16. I believe that other flash devices can be used but a check that the programmer does has to be disabled first. You could also use the newer EPCQ16 which costs less than the EPCS16 but this would require a different programming file with the boot loader changed to suit the EPCQ16.
I believe that Cyclone II can use similar SPI devices.


Frank

[`FRANK.C]

I have uploaded a pdf of how the analogue video is routed and switched to provide a modulator only mode. So far it appear to work well.

The pdf I have uploaded is a redrawn and cut down diagram showing only the analogue video circuit, as the complete Hedghog II diagram is large and difficult to follow.

Frank

[Jac Janssen]

Fellow Hedghog enthusiasts,

During use of the Hedghog I noticed some glitches in the picture.
These are the same with all versions of the software and in both HHs I built.
The occurrence looks more or less random, and it is difficult to photograph.
On the screen it looks a bit like a  flash in a line.
It is the same with external video or on the internal test card.
See attachments for 2 of those occurrences (it seems to happen sometimes more than once per second - probably more often when the HH is warm). The photos were taken from a short video I took with my ancient Canon A530 camera to capture it.

Please note that all geometrical distortions are in the monitor (I adapted it a bit for 405, but was original 625).
 
Did anyone else notice this too with his/her HH?

Jac
p.s. the horizontal black line in the photos is caused by my camera (exposure etc). There does not seem to be a vertical effect, just the tearing of lines.