04-11-2018, 05:39 PM
Since custom crystals are expensive there's a possible trick using the FPGA to synthesis the carrier frequencies for conventional modulators. There will be phase jitter from the discrete time oscillators but I don't know how much it would matter. Depending on the PLLs availabale on the chosen FPGA it may be possible to directly synthesise something close enough to the carrier frequencies with minimal phase jitter.
For those not familiar with DTOs in their simplest form they are just adders and accumulators. On each clock cycle you add the coefficient. So the output frequency is:
Fout = Fclock * Coefft/2^n
Where n is the number of bits in the accumulator. Maximum output frequency is half the input. The output is the adder overflow. More complex arrangements can be used to give ratios where the denominator isn't a power of 2. The accumulator output can also be sent to a sine table and DAC to synthesise a sine wave output. Typical numbers of bits range from 16 to 32 or more. Very simple to implement in a FPGA.
For those not familiar with DTOs in their simplest form they are just adders and accumulators. On each clock cycle you add the coefficient. So the output frequency is:
Fout = Fclock * Coefft/2^n
Where n is the number of bits in the accumulator. Maximum output frequency is half the input. The output is the adder overflow. More complex arrangements can be used to give ratios where the denominator isn't a power of 2. The accumulator output can also be sent to a sine table and DAC to synthesise a sine wave output. Typical numbers of bits range from 16 to 32 or more. Very simple to implement in a FPGA.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv