01-02-2016, 09:10 AM
I need to be able to sense the presence of mains as a 5V CMOS logic signal. Here's my first thoughts. Any comments?
The class Y cap and 22M resistor (it will be a VR37 series, rated at 2500V) are really belt and braces isolation, the current should be around 10uA with mains present. Since it will be feeding a CMOS load the high impedances won't be a problem.
Obviously if mains is reversed it won't work. This isn't a problem in my intended application but I suppose another 1n +22M to the other side of the mains would solve it.
The class Y cap and 22M resistor (it will be a VR37 series, rated at 2500V) are really belt and braces isolation, the current should be around 10uA with mains present. Since it will be feeding a CMOS load the high impedances won't be a problem.
Obviously if mains is reversed it won't work. This isn't a problem in my intended application but I suppose another 1n +22M to the other side of the mains would solve it.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv







