User Programmable Standards Converter

[ppppenguin]

I've done simple 50Hz<>60Hz conversion by frame duplication or dropping. On some movement it can look truly horrible, most of the time it isn't too bad. You see this sort of conversion artefact all the time when watching video material on a computer. There may be more than one implied frame rate conversion before it reaches your screen.

Incidentally, almost any 625/50 monochrome monitor will lock to 525/60. The line rates are almost identical (15625 vs 15734) and most sets will cope with 60Hz. Some will give reduced height. This was used as a trick to replay NTSC VHS tapes in PAL countries. 3.58MHz NTSC was transcoded to 4.43MHz PAL while leaving H and V rates unchanged. Most colour TVs could cope.

[`FRANK.C]

Incidentally, almost any 625/50 monochrome monitor will lock to 525/60. The line rates are almost identical (15625 vs 15734) and most sets will cope with 60Hz. Some will give reduced height. This was used as a trick to replay NTSC VHS tapes in PAL countries. 3.58MHz NTSC was transcoded to 4.43MHz PAL while leaving H and V rates unchanged. Most colour TVs could cope.

To my shame that fact escaped me  . Well as least until after getting it, I fed it with a 625 line signal and seen a locked line but rolling frame. Then the penny dropped!
I really should have known especially after doing all the work with the decoder and the video clock for both 625 and 525 being the same. I guess that PAL/NTSC had got into my brain. Still I am very happy to have it now and wouldn't part with it.

It is a Ikegami PM-K9. In the manual it states:
Horizontal: 15.75 kHz, Vertical: 60 Hz
Horizontal: 15.625 kHz, Vertical: 50 Hz

Frank

[ppppenguin]

15750Hz was the original 525 line line rate. When they went colour it was dropped by 1000/1001 giving 15734Hz. The reason was to do with the relationship between sound carrier and colour subcarrier though I don't know why. One had to move and it was decided not to risk having to retune the sound IF on millions of sets. The resulting 59.94Hz field rate has been a PITA ever since timecode was invented a few years later.

The common 13.5MHz sample frequency for 525 and 625 "601" digital TV was a fortunate coincidence. It subsequently became a slight PITA because the pixels aren't square and are different shape on each standard. For HDTV they settled on square pixels with different sample rates. 74.25MHz and 74.25 *1000/1001.

Amazingly the 59.94Hz related standards options have persisted even up to the highest 4K standards.

[Yellowtriumph]

15750Hz was the original 525 line line rate. When they went colour it was dropped by 1000/1001 giving 15734Hz. The reason was to do with the relationship between sound carrier and colour subcarrier though I don't know why. One had to move and it was decided not to risk having to retune the sound IF on millions of sets. The resulting 59.94Hz field rate has been a PITA ever since timecode was invented a few years later.

The common 13.5MHz sample frequency for 525 and 625 "601" digital TV was a fortunate coincidence. It subsequently became a slight PITA because the pixels aren't square and are different shape on each standard. For HDTV they settled on square pixels with different sample rates. 74.25MHz and 74.25 *1000/1001.

Amazingly the 59.94Hz related standards options have persisted even up to the highest 4K standards.

This article gives a good account as to why the frame rate needed to be altered with the introduction of NTSC Color.

https://www.tvtechnology.com/opinions/wi...nd-of-5994

[Spot Wobble]

Many thanks for the link to the NTSC colour article - I now find the subject (slightly) clearer

Many thanks,

Francis

[`FRANK.C]

pictures below is of the latest prototype.
The prototype board is just used as a temporary bracket to hold the display in a position that it can be seen. Otherwise the display just flaps about and usually ends up face down.
It looks similar to the last one but they are quite a number of circuit changes.
The microcontroller is changed from a 18LF26K22 to a 18F26K22 and is now operating with 5V logic levels.
I was using the 18LF26k22 with 3.3V logic levels to match in with the 3.3V logic levels of the FPGA.
But the LCD display I decided to use is a 5V type and it didn't take kindly to the 3.3V logic levels from the 18LF26K22 resulting with some corrupted charters on the display.
Display NHD-02161Z-FSY-YBW-C

Writing twice to the display gave satisfactory results but I didn't think it good enough to leave it like that so I decided to change the microcontroller to 5V logic.
As communication is only one way between the microcontroller and the FPGA it was easy to drop the logic levels from 5V to 3.3V using potential dividers to suit the FPGA.

Because the audio gets fed to both modulator chips dependant on what standard is selected another Audio Gain pot would be needed for the second modulator.
Instead of using a second pot I have removed the one that was there and replaced it with a Digipot. With the Digipot a different level can be set for each preset if needed.
Digipot  MCP40D18T-503E/LT


I am also trialling a DC to DC converter instead of the LM7805 if it don't cause any problems it will be a keeper as it has dramatically reduced heat dissipation.
It has the same footprint as the LM7805 so is easily converted if any issues arise.
DC to DC converter OKI-78SR-5/1.5-W36-C

Frank

[Murphyv310]

Hi Frank.
Great work you have done.
Question. Once you have finalised this project do you have plans to getcl them made?
I'm interested if you do.

[Freya]

Looking Great Frank, hope you have had A good Christmas.
Does the LCD use the whole height of the front panel plastic, or would it need a window cut out for the visible area. just thinking of mounting ideas.
If you do make any further PCB revisions could you move the 100nF and 10uF caps on the 3.3 volt reg further apart, its tricky soldering them so close together and being neat.

Stephen

[ppppenguin]

The whole business of 5V, 3.3V, and sometimes lower voltage, logic can be a real PITA. All current FPGAs are 3.3V max and won't withstand 5V on their inputs. Some of the more sophisticated ones may be even lower voltage. Because they have clamp diodes to 3.3V and 0V you can do the interface from 5V with just a series resistor to limit the current. Allowing for the clamp diode about 1K will work to limit the current to about 1mA. But only at low speed as the stray C will get you.

I've looked at the data sheet for the display module and logic HI is 0.7*VCC, or 3.5V when running at 5V. In practice they will work down to not much above 2.5V but there's no guarantee. If you're careful you could run the display at 4.8V, the minimum allowed and push the 3.3V rail a touch high to get guaranteed logic levels. All a bit tricky and marginal. Another wheeze would be to power the display from about +4.5V and --0.5V. This would just about give you guaranteed logic levels but you'd need to create a -ve supply.

If it's just I2C that needs to be interfaced you can get 5V<>3V3 I2C converter chips. Another trick is to pull SCLand SDA up to 5V. Most 3V3 parts won't mind this due to limited current and clamp diodes. Logic HI will get to about 4V which is good enough. This will also work if you simulate open collector outputs on a FPGA and use external pullups to +5V. That's done by tristating the output for logic HI.

The digital pots are amazingly cheap! 11p+VAT each from RS in the UK.

I like the look of those drop-in switchmode 7805 regs. What you can't do is put a diode in the 0V leg to jack the voltage up a bit. This is a trick I've used with ordinary 7805 etc on occasion.

[`FRANK.C]

Hi Trevor
I wont be getting any made myself.
When I have it finished I will be putting the details of it up on my website as I have done for the other Hedghog's
If you do want one I believe Stephen will oblige

Hi Stephen
It will need a window cutting out. If you follow the link to Mouser there is a data sheet for it that can be downloaded. Which has a dimensional drawing of the display.

Hi Jeffrey
Speed is not a problem with the communications between microcontroller and FPGA. I can slow it down as far as is needed for solid communications without any big difference in how it preforms.
It only communicates when a preset is changed and then just sends 50 bytes of information.
The Digipots are good value they have just 127 steps but that is plenty for this application.

Frank