405 to 625 conversion

[`FRANK.C]

I got some time the evening and successfully extracted the odd/even field from the bypassed video by counting the number of whole lines between the broad pulses.

The settings of register 0Dh that I am using is "01001111".

YCbCr data path bypass
Decimation filter output connects directly to the YCbCr output pins.
HBLANK area is replaced with ITU-R BT.656 digital blanking.

YCbCr output format
8-bit ITU-R BT.656 interface with embedded sync output

Going by the settings of the register I think the burst that can bee seen may be the digital blanking.

Frank

[ppppenguin]

Well done. When you're trying to do non-standard things with a complex chip you have to be prepared to try oddball looking settings.

[`FRANK.C]

Made some progress. I got the interpolater finished it is a 2 line interpolater using 3 line stores of two port RAM. 2 lines are read from while the third is written to. They are rotated at each 405 line.  You could probably get away with 2 line stores but the FPGA has plenty of memory and 3 makes it easier to manage.

The decoder was producing the H sync too late on each line which had the effect of cropping the beginning of the lines.
Adjusting the H sync position and the AVID start and stop positions in the decoder  resolved that.

The decoder has a 9 bit ADC at its input but the is no way I can find to access the 9 th bit.

I am using a colour monitor to view the output it has a good sharp image but is not at all photogenic. Any photo I took of it came out pretty awful with a lot of pattering on it.
Picture below of the 625 output of the converter is off a TV

Frank

[Jac Janssen]

Very impressive results Frank (and Jeffrey as well!)

Jac

[ppppenguin]

Pair of my 405 to 625 converters in their chassis, almost ready for their new home with the BECG: https://becg.org.uk/

I need to hack a bit of 8051 assembler and blast everything into an EPROM.

These boards and chassis were leftovers from a professional design I did years ago for G2 Video Systems. The design was intended for flexible video processing and that's been proven again with this project. Some things are a nuisance. For example the newest Xilinx tools that support the XC2S200 is version 10.1. This won't run in anything later than Windows XP. So it has to be a virtual machine.

[`FRANK.C]

Thanks Jac.

Jeffrey
That's an impressive looking dual converter it all fits very well together and wont take up much space..
I think I can see where the crystal you had to remove used to live beside the power plug.
I take it that the firmware is stored in the EPROM.

Frank

[ppppenguin]

The Xilinx boot, 8051 program and any test patterns are all stored in the EPROM. I've written a simple linker that put them all together.

The empty xtal slot you can see on the main PCB was never used. Can't remember why it's there at all. The xtal I removed was on one of the sub-boards. Not visible in the photo.

[ppppenguin]

Made some mods today so that the 405 line input can be put in a window on the 625 output. The interpolator is switched off. This allows somebody with a digital video effects unit to do their own interpolation (it would be called zoom in this context) which may well be better than what I'm doing. This is probably the right approach for recovering archive tapes.

The photo is awful due to stray light, compression etc. The picture on the screen is excellent.

[peter scott]

That does look excellent!

Peter

[ppppenguin]

Thanks, Peter. For the last couple of days I've been banging my head on a brick wall trying to get the thing to work on its own software as against with debug computers connected. I don't like writing x51 assembler but fortunately most of that was already done for past projects.

I got out the EPROM emulator and found that I could still remember how to use the odd batch files etc I'd written years ago. The Xilinx would load and things would substatially come to life. Except that neither the SAA7118 decoder nor ADV7171 encoder would program via I2C. Definite activity on the I2C bus and those bits of x51 code were old and well proven. Much frustration. Eventually the penny dropped. There was no clock going to the SAA7118, the new reduced frequency clock that's the key to the whole project. Why? It was loading an old Xilinx file (from my 625 to 405 experiments becuase I'd omitted a parameter when calling the batch file. I'd typed:

emg h1

Which links the x51 object code, xilinx binary and a test card C binary, then sends the whole lot to the EPROM emulator. h1 is the name of the x51 project. What I'd forgotten was the 2nd parameter, the name of the xilinx project. I rapidly relearned that if a batch file is missing a parameter there's no warning, it just treats it as null.

emg h1 h1

The xilinx project is also called h1. And everything worked.

Much joy.

I hope it's now a tidying job. HF response seems a bit down. Need to see if it's the SAA7118 or something else. The output side is OK because I checked with digital multiburst stored in the Xilinx. I'll put multiburst into the Aurora, check the output on a scope and see what my converter makes of it. A future project might be a high quality FPGA based 405 line test pattern generator.