405 to 625 conversion

[`FRANK.C]

Hi Jeffrey
Great work!
Looks like it will be a nice neat solution.

Frank

[ppppenguin]

Having done the hard stuff, I tidied up the VHDL and it's stopped working. All the new sync stuff is still OK - I can see it on test points - but somehow the video isn't being written to the framestore. All the pulses that drive the framestore seem to be there and I can write a test pattern to the framestore from the debug system.

It's obviously something silly but finding it is driving me mad. Probably best to leave it an come back in the morning.

[`FRANK.C]

Hi Jeffrey
Been there many times always best to leave it for a new day when it all becomes clear. But it is not always to do that.

Frank

[ppppenguin]

Got pictures back. The main framestore is divided into 4 quadrants, each of which can hold a whole frame of video. For some reason I was writing to quadrant 1 and reading from quadrant 0. I have no idea how this happened. The intention was to read and write in quadrant 1.

PS: Found it! If the input is absent the output can be optionally switched to an image stored in quadrant 0. I'm not doing input failure detection at the moment and had accidentally forced it to input absent instead of input present during the tidy up. This was compounded by a debug setting allowing auto switch on input failure.

Moral: It's easy when you find it.

[Mike Watterson]

Anyway, I'm finding this thread very interesting, especially now that I'm more inclined to read about Electronics than do much. Writing is very time consuming as you also need to read lots.
I was tempted to order one of those newer sync sep chips, I do have a couple of the old DIL common ones. I have little SOP adapter boards for two pitches of 14 lead devices. The newer TI/Nat Semi chip seems to be about £12 on eBay from China. I stopped using Farnell/RS about 10 years ago due to low volume/postage issues. It was different ordering parts for the day job.

Glad you found the bug.

[ppppenguin]

The LM1881 is fine for most purposes. When you need precision sync separation and something that will work with trisync (as used on HD analogue) you need something better. I look back over my older designs and see precision sync separators that I've designed from discretes. No point now when good chips are around.

Glad I managed to do my 405 to 625 conversion without extra hardware. The only hardware mod was removing the 24.576MHz xtal and adding a wire link. Not sure if this will be feasible with the TVP5150 decoder as used on Aurora and Hedghog. Lowering the clock frequency works but getting good H and V sysncs looks harder.

Now to resolve the remaining problems. Horizontal timing should be easy. Finding the flaw in the interpolator somewhat less so. I also need to consider whether the output should be genlocked to a colour black reference. This would be useful if a 405 source needs to be fed into a conventional vision mixer. May not be worth the effort. Can always use a framestore synchroniser if that's occasionally needed.

I did an audit of the various input and output modules I have around. Plenty of analogue input, plenty of SDI input and output. Just 2 analogue output. So I'll probably go with SDI output, on the grounds that SDI to analogue converters are cheap and readily available. In a professional environment SDI is standard anyway. Actually HD-SDI has been the norm for some time but converter boxes are not expensive. I use a Decimator MD-HX https://cvp.com/product/redbyte_design_dd-hx_md-hx which happily handles any SDI I care to throw at it.

[Mike Watterson]

The LM1881 is fine for most purposes. When you need precision sync separation and something that will work with trisync (as used on HD analogue) you need something better. I look back over my older designs and see precision sync separators that I've designed from discretes. No point now when good chips are around.

I'm more likely to be looking at VGA and progressive component on my scope than doing anything else. It's a Hameg so not great TV sync and no delay timebase.
I've been offered a working Closed Caption decoder designed to go between VHS and TV. I'm curious as to what it does. I remember in BBC to "fix" bad sync 625 tape playback they discovered that putting a Sound-in-syncs box inline "fixed" it.
I had a Salora TV once that couldn't display some Sky Setbox programs (We "rented" a sky Box Office film) and some pre-recorded VHS tapes. I'm sure it was the evil analogue anti-piracy scheme.

I support copyright, but all anti-piracy schemes (Analogue, CSS, HDCP, DRM, Steam etc) just cause consumer issues, add to cost (royalties) and don't stop commercial pirates.

I wonder how the FPGA or LM1881 or the various converter ICs cope with analogue anti-piracy schemes on 625. At least not a problem with ANY 405 line source!

[ppppenguin]

I can only speak for the SAA7118 PAL/NTSC decoder and macrovision. It tolerates and detects macrovision. In the products I designed we ignored macrovision.

The LM1181 shouldn't mind macrovision.

I once designed a Sound-in-Sync stripper. In other words get rid of SiS from a video signal. I don't have the circuit immediately to hand but ISTR the sync separator was a bit special. It had to find the leading edge of sync and then ignore everything else until the trailing edge.

Photo shows latest results. H timing was correctable in the SAA7118, just trim the appropriate register settings. Interpolation is still horrible as you can see.

Just realised I might need to play with brightness and contrast. It's not miles out but I was originally using the SAA7118 in its 656 (601 with digital sysncs) mode. Assuming the picture to sync ratio on the input was correct this made the brightness and contrast correct by design. But now I'm taking raw ADC output and haven't yet established the black and white levels. I think black is at 60h from my sync separator experiments. What I won't have is the SAA7118's built-in contrast and brightness controls. Correcting black level is easy, just an adder. There may be facility to tweak the AGC on the ADC. If not it means a multiplier which is a lot of logic in this FPGA. Perhaps not too bad as one input should be a constant which can massively reduce the logic required. Might be able to do it in a BRAM (block RAM) as I actually have some to spare. They're normally a precious resource but I'm only using 7 out of the 14 available. In virtually every FPGA deisgn I've ever done BRAM has been a problem.

PS: Bunged PLUGE through the system. Black is 130mV above blanking and black to white is only 470mV. The ADC isn't using a lot of its dynamic range. The digital levels are about 58 for black and 203 for white. The 601 standard is 16 for black, 235 for white.

[`FRANK.C]

Hi Jeffrey
Looks good. Great result so far.

Frank

[ppppenguin]

I've done the brightness and contrast, including limiters to prevent digits wrapping round from white to black and vice versa. in "601" black level is 16 and white is 235. 1-15 are available for signals that go a little below black. I've simplified my logic by clipping anything below black. So for example a true PLUGE signal won't be properly reproduced. At the other end I've allowed the full overload range above white.

Calling a day until Monday now. Main thing left to tackle is the interpolator which is definitely unhappy. From what I remember when I did 625 to 405, the interpolator was happy with a wide range of vertical shrink and expand with the same set of coefficients.