10-02-2023, 07:48 PM
Hi Jeffrey
Having to declare the write enables as 1 bit SLV is one of those things that if you know it isn't a problem but if you don't you could spend hours tearing your hair out.
What I am using now for the time redistribution fifo is below.
The BRAM is in 4k blocks and SB_RAM2048x2 is a privative foe 2048 X 2 RAM. It appears to synthesize and work ok.
Another thing I noticed on the RTL viewer and also on the technology view was that the registers on the input and output pins were not been used. The signals passed through them without any clock.
As far as I understand they should be used by default. I can put them working by using primitives.
Frank
Having to declare the write enables as 1 bit SLV is one of those things that if you know it isn't a problem but if you don't you could spend hours tearing your hair out.
What I am using now for the time redistribution fifo is below.
The BRAM is in 4k blocks and SB_RAM2048x2 is a privative foe 2048 X 2 RAM. It appears to synthesize and work ok.
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library work;
use vcomponent_vital_2.all;
entity fifo_tr is
port (
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic;
rdclk : in std_logic;
wrclk : in std_logic;
data : in std_logic_vector (7 downto 0); -- data in
q : out std_logic_vector (7 downto 0)); -- data out
end fifo_tr;
architecture rtl of fifo_tr is
signal WR_ADD : std_logic_vector(10 downto 0);
signal RD_ADD : std_logic_vector(10 downto 0);
signal DATAin1 : std_logic_vector(1 downto 0);
signal DATAin2 : std_logic_vector(1 downto 0);
signal DATAin3 : std_logic_vector(1 downto 0);
signal DATAin4 : std_logic_vector(1 downto 0);
signal DATAout1 : std_logic_vector(1 downto 0);
signal DATAout2 : std_logic_vector(1 downto 0);
signal DATAout3 : std_logic_vector(1 downto 0);
signal DATAout4 : std_logic_vector(1 downto 0);
signal ACLR_B : std_logic;
signal ACLR_C : std_logic;
begin
u1 : SB_RAM2048x2 port map ( RDATA => DATAout1, RADDR => RD_ADD, RCLK => rdclk, RCLKE => '1', RE => '1', WADDR => WR_ADD,
WCLK=> wrclk, WCLKE => '1', WDATA => DATAin1, WE => wrreq );
u2 : SB_RAM2048x2 port map ( RDATA => DATAout2, RADDR => RD_ADD, RCLK => rdclk, RCLKE => '1', RE => '1', WADDR => WR_ADD,
WCLK=> wrclk, WCLKE => '1', WDATA => DATAin2, WE => wrreq );
u3 : SB_RAM2048x2 port map ( RDATA => DATAout3, RADDR => RD_ADD, RCLK => rdclk, RCLKE => '1', RE => '1', WADDR => WR_ADD,
WCLK=> wrclk, WCLKE => '1', WDATA => DATAin3, WE => wrreq );
u4 : SB_RAM2048x2 port map ( RDATA => DATAout4, RADDR => RD_ADD, RCLK => rdclk, RCLKE => '1', RE => '1', WADDR => WR_ADD,
WCLK=> wrclk, WCLKE => '1', WDATA => DATAin4, WE => wrreq );
-------------------------------------------------------------------------------------------------
------------------------------------ processes --------------------------------------------------
-------------------------------------------------------------------------------------------------
process (wrclk)
begin
if rising_edge(wrclk) then
DATAin1 <= data(1 downto 0);
DATAin2 <= data(3 downto 2);
DATAin3 <= data(5 downto 4);
DATAin4 <= data(7 downto 6);
if aclr = '1' then
WR_ADD <= "00000000000";
else
if (wrreq = '1') then
WR_ADD <= WR_ADD + '1';
end if;
end if;
end if;
end process; --wrclk
process (ACLR_C, aclr)
begin
if ACLR_C = '1' then ACLR_B <= '0';
elsif rising_edge(aclr) then ACLR_B <= '1';
end if;
end process; --ACLR_C, aclr
process (rdclk)
begin
if rising_edge(rdclk) then
if (rdreq = '1') then
RD_ADD <= RD_ADD + '1';
if ACLR_B = '1' then
ACLR_C <= '1';
RD_ADD <= "00000000000";
else
ACLR_C <= '0';
end if;
end if;
q(1 downto 0) <= DATAout1;
q(3 downto 2) <= DATAout2;
q(5 downto 4) <= DATAout3;
q(7 downto 6) <= DATAout4;
end if;
end process; --rdclk
end rtl;Another thing I noticed on the RTL viewer and also on the technology view was that the registers on the input and output pins were not been used. The signals passed through them without any clock.
As far as I understand they should be used by default. I can put them working by using primitives.
Frank
