09-02-2023, 06:50 PM
I have spent some more time on this.
The time redistribution memory was inferred and wouldn't synthesize as I wanted. Only the write clock was connected to the BRAM. The read clock only connecting to some registers on the output from the memory.
This I could see on the RTL viewer.
I spent a lot of time fruitlessly trying to get the Memory building tool working and eventually had to give up.
The only option that I could see was to use primitives. I hadn't used them before so it took a while to get to grips with them.
But I got the memory built with them and it now synthesizes as I want.
Frank
The time redistribution memory was inferred and wouldn't synthesize as I wanted. Only the write clock was connected to the BRAM. The read clock only connecting to some registers on the output from the memory.
This I could see on the RTL viewer.
I spent a lot of time fruitlessly trying to get the Memory building tool working and eventually had to give up.
The only option that I could see was to use primitives. I hadn't used them before so it took a while to get to grips with them.
But I got the memory built with them and it now synthesizes as I want.
Frank
