03-02-2023, 11:19 PM
I have fitted a 405 line test card into a programming image. The test card and the sync generation for it was much larger than the converter.
I had to whittle a good bit of it away to make it fit.
I also had a bit of a play with the cold boot. It works very well.
The PIC sequences the selection of the image and the resetting of the FPGA.
The cold boot will be useful and will allow the test card to be used.
One thing that struck me was how small the programming file for the iCE40HX1K is compared to others.
The programming file for the EP4CE6E that is used in the Hedghog II is 2 MB
The file for the EP2C5 used in the Hedghog is 512 KB
The file for the iCE40HX1K is a just 32KB
Frank
I had to whittle a good bit of it away to make it fit.
I also had a bit of a play with the cold boot. It works very well.
The PIC sequences the selection of the image and the resetting of the FPGA.
The cold boot will be useful and will allow the test card to be used.
One thing that struck me was how small the programming file for the iCE40HX1K is compared to others.
The programming file for the EP4CE6E that is used in the Hedghog II is 2 MB
The file for the EP2C5 used in the Hedghog is 512 KB
The file for the iCE40HX1K is a just 32KB
Frank







