29-01-2023, 02:40 PM
The PCBs arrived and I got one built.
I can programme the FPGA but the Flash memory wont programme for me. I will have to spend some time later to find out what the problem is.
The chips that can be seen on the bottom side of it are PIC, FPGA, Video decoder and Video amp.
When first tried. I used the files I tested in the Hedghog they included the inferred memories, 2 line interpolater and 4 X oversampling on the output.
When tested in the Hedghog they worked fine without using any constraints.
To reduce the logic to a minimum I didn't use an interpolator and just used line dropping. I also removed the 4 X oversampling.
The resultant conversion was full of glitches and there was line jitter at approximately 2 Hz.
Constraining the clocks and reducing the the clock for the DTO that produces the video output clock from 218 MHz to 108 MHz cured the line jitter.
The glitches were also reduced but some still remained.
Constraining another 9 MHZ clock that I had missed gave a clean conversion.
The picture of the test card below is of it working.
I am using a PSC as a signal source. It is a 2 line converter with 4 X oversampling on the output. With no options not even equalising pulses.
The line delay and time redistribution memories are inferred. There is a wizard that should build them but it just wont save the built files for me.
Frank
I can programme the FPGA but the Flash memory wont programme for me. I will have to spend some time later to find out what the problem is.
The chips that can be seen on the bottom side of it are PIC, FPGA, Video decoder and Video amp.
When first tried. I used the files I tested in the Hedghog they included the inferred memories, 2 line interpolater and 4 X oversampling on the output.
When tested in the Hedghog they worked fine without using any constraints.
To reduce the logic to a minimum I didn't use an interpolator and just used line dropping. I also removed the 4 X oversampling.
The resultant conversion was full of glitches and there was line jitter at approximately 2 Hz.
Constraining the clocks and reducing the the clock for the DTO that produces the video output clock from 218 MHz to 108 MHz cured the line jitter.
The glitches were also reduced but some still remained.
Constraining another 9 MHZ clock that I had missed gave a clean conversion.
The picture of the test card below is of it working.
I am using a PSC as a signal source. It is a 2 line converter with 4 X oversampling on the output. With no options not even equalising pulses.
The line delay and time redistribution memories are inferred. There is a wizard that should build them but it just wont save the built files for me.
Frank
