05-01-2023, 04:38 PM
I have used the iCEcube2 tools to synthesize a standards converter in the CE40HX1K
I altered the Hedghog files that I had considerably. I pruned them back to the essential items.
I ended up with a 2 line interpolater, 2 multipliers, a 1 line FIFO, most of the rest of the memory is used in the time redistribution memory.
It wont do the programming of the TVP5010 or modulators.
The video output is not over sampled.
Resource Usage Report for HEDGHOG_L_1
Mapping to part: ice40hx1ktq144
Cell usage:
GND 4 uses
SB_CARRY 342 uses
SB_DFF 52 uses
SB_DFFE 203 uses
SB_DFFESR 23 uses
SB_DFFESS 5 uses
SB_DFFR 2 uses
SB_DFFSR 88 uses
SB_DFFSS 1 use
SB_GB 6 uses
SB_RAM1024x4 2 uses
SB_RAM2048x2 12 uses
VCC 4 uses
pll 1 use
SB_LUT4 749 uses
I/O ports: 18
I/O primitives: 18
SB_GB_IO 1 use
SB_IO 17 uses
I/O Register bits: 0
Register bits not including I/Os: 374 (29%)
RAM/ROM usage summary
Block Rams : 14 of 16 (87%)
Total load per clock:
HEDGHOG_L_1|CK_27_MHZ: 1
HEDGHOG_L_1|CK_PLL_216_MHZ_inferred_clock: 1
in_625|CLK_derived_clock: 134
@S |Mapping Summary:
Total LUTs: 749 (58%)
Distribution of All Consumed LUTs = LUT4
Distribution of All Consumed Luts 749 = 749
Mapper successful!
I have looked at it using the RTL viewer and it appears to be all there.
It looks promising but I take all of the above with a pinch of salt as I know that just missing out on one signal can result in a huge chunk of the circuit not getting synthesized.
Until I try it in a circuit I wont really know if it will work
So I have ordered a development board they are not expensive.
https://www.olimex.com/Products/FPGA/iCE...e-hardware
Frank
I altered the Hedghog files that I had considerably. I pruned them back to the essential items.
I ended up with a 2 line interpolater, 2 multipliers, a 1 line FIFO, most of the rest of the memory is used in the time redistribution memory.
It wont do the programming of the TVP5010 or modulators.
The video output is not over sampled.
Resource Usage Report for HEDGHOG_L_1
Mapping to part: ice40hx1ktq144
Cell usage:
GND 4 uses
SB_CARRY 342 uses
SB_DFF 52 uses
SB_DFFE 203 uses
SB_DFFESR 23 uses
SB_DFFESS 5 uses
SB_DFFR 2 uses
SB_DFFSR 88 uses
SB_DFFSS 1 use
SB_GB 6 uses
SB_RAM1024x4 2 uses
SB_RAM2048x2 12 uses
VCC 4 uses
pll 1 use
SB_LUT4 749 uses
I/O ports: 18
I/O primitives: 18
SB_GB_IO 1 use
SB_IO 17 uses
I/O Register bits: 0
Register bits not including I/Os: 374 (29%)
RAM/ROM usage summary
Block Rams : 14 of 16 (87%)
Total load per clock:
HEDGHOG_L_1|CK_27_MHZ: 1
HEDGHOG_L_1|CK_PLL_216_MHZ_inferred_clock: 1
in_625|CLK_derived_clock: 134
@S |Mapping Summary:
Total LUTs: 749 (58%)
Distribution of All Consumed LUTs = LUT4
Distribution of All Consumed Luts 749 = 749
Mapper successful!
I have looked at it using the RTL viewer and it appears to be all there.
It looks promising but I take all of the above with a pinch of salt as I know that just missing out on one signal can result in a huge chunk of the circuit not getting synthesized.
Until I try it in a circuit I wont really know if it will work
So I have ordered a development board they are not expensive.
https://www.olimex.com/Products/FPGA/iCE...e-hardware
Frank
