Lattice iCE40HX1K FPGA

[ppppenguin]

I implemented a standards converter in a Xilinx XC2S200 which has just over 5000 logic cells.  I think I was being fairly clever about the interpolation multiplier, multiplexing all 4 lines through it at 4x clock. The design used SDRAM framestores. All interpolation was after the framestores since I had enough memory bandwidth to make it look like a multiport RAM. If you're using block RAM to do  internal linestores then you're likely to run out of that resource before anything else.

The mapping report said:
Logic Distribution:
    Number of occupied Slices:                      1,072 out of  2,352  45%
    Number of Slices containing only related logic:  1,072 out of  1,072  100%
    Number of Slices containing unrelated logic:        0 out of  1,072    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        1,198 out of  4,704  25%
      Number used as logic:                    1,041
      Number used as a route-thru:                145
      Number used as Shift registers:              12
  Number of bonded IOBs:          202 out of    284  71%
      IOB Flip Flops:                            149
      IOB Latches:                                  8
  Number of Block RAMs:              8 out of    14  57%
  Number of GCLKs:                  3 out of      4  75%
  Number of GCLKIOBs:                3 out of      4  75%
  Number of DLLs:                    2 out of      4  50%

I think a synthesised 8x8 multiplier uses about 64 cells. Needs a fair bit of internal pipelining to work at video speeds.

I've attached all the VHD files from my design but I think I sent you these long ago. It will take a fair but of dredging my own memory banks to remember much more.

This was the design I later adapted to do 405 to 625 conversion. The hardware is a board I designed for a professional cliient some years ago. I happen to have a few around.

PS: Don't try to design a multiplier yourself. I've done this on older FPGAs before there were tools like Coregen to do the job for you. It's a lot of work to design and debug.

PPS: I've totally lost touch with the FPGA market. Haven't done any real design work for years. Xilinx and Altera have both been bought by huge companies (Intel and AMD) who I suspect aren't interested in small devices anymore. So you're loking at 2nd tier makers like Lattice.