User Programmable Standards Converter

[ppppenguin]

Thinking about using external SRAM for a framestore, if some ports are mutually synchronous (for example reading from 4 successive lines) then there is no absolute need for overhead for port switching., just like with internal FPGA RAM. However this requires that the SRAM clock is synchronous to those ports. For example if you're reading 4 ports at 13.5MHz then clocking the SRAM at 108MHz would make sense. You can read the 4 ports on succesive cycles of 108MHz leaving adequate time to switch to a write port that isn't synchronous.