04-02-2020, 08:57 AM
(This post was last modified: 04-02-2020, 08:58 AM by ppppenguin.)
When I was at Crossfield as a fairly junior engineer c1984 one of my jobs was to redesign a video graphics generator. The whole system was built on PCBs about 15" square with 3x DIN 96 pin connectors. The PSUs were 200A at +5V for the TTL etc and 160A at -5.2V for the ECL. The processing side was AMD bitslice but my job was the other side of the cage. 1Kx1K 32 bit (RGB + alpha) graphics, very exotic for the time. RAM was made from 8(?) cards full of 64Kx1 DRAM, the video side logic was a mix of TTL and ECL, the pixel clock was 45MHz.
I managed to halve the number of RAM cards by increasing the chip density on the PCB. 256K DRAM were becoming available at the time but didn't offer any advantage as we needed a very wide memory bus to get the data throughput. I also condensed 3 cards full of ECL and TTL into 1. Partly by using newfangled 22V10 PAL devices, partly by better design.
We did thermal management by brute force - massive fan tray at the bottom of the cage.
Can't remember what we used for 8 bit DACs at 45MHz. Probably something by TRW.
I managed to halve the number of RAM cards by increasing the chip density on the PCB. 256K DRAM were becoming available at the time but didn't offer any advantage as we needed a very wide memory bus to get the data throughput. I also condensed 3 cards full of ECL and TTL into 1. Partly by using newfangled 22V10 PAL devices, partly by better design.
We did thermal management by brute force - massive fan tray at the bottom of the cage.
Can't remember what we used for 8 bit DACs at 45MHz. Probably something by TRW.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
