16-11-2019, 05:00 PM
(This post was last modified: 16-11-2019, 05:02 PM by Mike Watterson.)
A PIC, the old philips RDS chip and take FM decoder signal where it goes to Stereo decoder. Not possible on modern "all in one" radios that have stereo decoder inside RF chip.
Without the HW chip which takes 57kHz in and gives TTL 1170 bps out, it's not possible without serious DSP on a much higher power ARM. The basic Ardunio is an Atmel, now owned by Microchip who do PIC. I have the decoding code for the PIC and also the LCD panel code.
The Ardunio like boards that take the same shields and have decent ARM are not as good as Raspberry Pi and would work out more. For any DSP solution you'd want at least 192 kHz sampling (96kHz is Nyquist unless doing I & Q which needs two 90 degree clocks, two signals or 384kHz) and an older radio where there is access to signal at input of the Stereo Decoder. Of course the newer all in one FM chip radios usually do RDS also, anyway.
Only the bit to get the 1170 bps data from the modulation on the 57kHz carrier (approx?) needs DSP. After that it's just implementing the public RDS spec. The old Philips DIL IC has an internal switched capacitor filter for 57kHz, a sort of hybrid Analogue / Digital signal processing maybe first used by Mitel in DTMF decoders that were single chip and outperformed previous C.O. systems. I think equivalents still made. MT8870?
I think there may also have been some sort of programmable filter using the technique, which power wise out performs an FPGA (hardware DSP) or a decent ARM doing DSP in software. Volume designs based on the FPGA take little power and can be made directly from the design file, if you have $500,000 to spare. But then if you sell 10 million gadgets the cost might be $2 each inc the $500,000 NRE, whereas FPGA is in comparison maybe 100x cost and 100x power usage. CPU DSP in software is very limited in speed x complexity compared to FPGA and can use more power than an FPGA at higher frequencies or complexity.
Without the HW chip which takes 57kHz in and gives TTL 1170 bps out, it's not possible without serious DSP on a much higher power ARM. The basic Ardunio is an Atmel, now owned by Microchip who do PIC. I have the decoding code for the PIC and also the LCD panel code.
The Ardunio like boards that take the same shields and have decent ARM are not as good as Raspberry Pi and would work out more. For any DSP solution you'd want at least 192 kHz sampling (96kHz is Nyquist unless doing I & Q which needs two 90 degree clocks, two signals or 384kHz) and an older radio where there is access to signal at input of the Stereo Decoder. Of course the newer all in one FM chip radios usually do RDS also, anyway.
Only the bit to get the 1170 bps data from the modulation on the 57kHz carrier (approx?) needs DSP. After that it's just implementing the public RDS spec. The old Philips DIL IC has an internal switched capacitor filter for 57kHz, a sort of hybrid Analogue / Digital signal processing maybe first used by Mitel in DTMF decoders that were single chip and outperformed previous C.O. systems. I think equivalents still made. MT8870?
I think there may also have been some sort of programmable filter using the technique, which power wise out performs an FPGA (hardware DSP) or a decent ARM doing DSP in software. Volume designs based on the FPGA take little power and can be made directly from the design file, if you have $500,000 to spare. But then if you sell 10 million gadgets the cost might be $2 each inc the $500,000 NRE, whereas FPGA is in comparison maybe 100x cost and 100x power usage. CPU DSP in software is very limited in speed x complexity compared to FPGA and can use more power than an FPGA at higher frequencies or complexity.
