04-06-2019, 04:27 PM
From experience I can assure you that interpolating between spatially adjacent lines on odd and even field works fine on static images. And looks horrible as soon as anything moves. The Pineapple converter used framestores. It had a switch to choose frame or field based interpolation. Interpolating between lines on different fields was utterly hopeless on anything that moved.
I've done 625/50 <> 525/60 conversion using 4 fields and 4 lines. Roughly equivalent to the BBC/McMichael ACE. It can work very well, but nothing like as good as modern motion compensated conversion. Good de-interlacing is also hard. Look at some LCD TVs to see the horrible mess they make of slow movement.
I don't know if the AL422 is still available. It's a good chip and very easy to use - I've used it professionally. But it lacks flexibility in a standards converter. In my experimental 625>405 converter I used SDRAM. A pair of these giving a 32 bit data bus. Using some fairly clever logic it looks like there's a video input and 4 separate video outputs. All of which have more or less free addressing. This allows me to write 625 video and read 4 different lines of 405 for the interpolator. No separate line stores. In fact I multiplexed the 4 reads on to a single bus running at 4x the 405 clock speed. This also allowed me to use only 1 multiplier to make a 4 line interpolator. A big advantage since I was using an ancient Xilinx FPGA (Spartan 2, XC2S200) which didn't have dedicated multipliers.
I've done 625/50 <> 525/60 conversion using 4 fields and 4 lines. Roughly equivalent to the BBC/McMichael ACE. It can work very well, but nothing like as good as modern motion compensated conversion. Good de-interlacing is also hard. Look at some LCD TVs to see the horrible mess they make of slow movement.
I don't know if the AL422 is still available. It's a good chip and very easy to use - I've used it professionally. But it lacks flexibility in a standards converter. In my experimental 625>405 converter I used SDRAM. A pair of these giving a 32 bit data bus. Using some fairly clever logic it looks like there's a video input and 4 separate video outputs. All of which have more or less free addressing. This allows me to write 625 video and read 4 different lines of 405 for the interpolator. No separate line stores. In fact I multiplexed the 4 reads on to a single bus running at 4x the 405 clock speed. This also allowed me to use only 1 multiplier to make a 4 line interpolator. A big advantage since I was using an ancient Xilinx FPGA (Spartan 2, XC2S200) which didn't have dedicated multipliers.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
