FPGA System A modulator

[ppppenguin]

The published specs are worst case limits. The equipment is working at room temperature and accurate voltages which helps. I may also be lucky. Some years ago I was experimenting with a design using a Xilinx FPGA (original Virtex so that's a good few years ago, probably c2000) and SDRAM. I needed the SDRAM to run at 133MHz but decided to inject a variable clock from a signal generator and see where it gave up. Went to almost 170MHz which was reassuring. Don't know what gave up first.

At the moment this is all I've got running:

Code:

case RF_OUT_SWITCH is when "000" => RF_OUT <= not AUDIO_SINE(15) & AUDIO_SINE(14 downto 6); when "001" => RF_OUT <= not VISION_CARRIER(13) & VISION_CARRIER(12 downto 4); when "010" => RF_OUT <= not SOUND_CARRIER(13) & SOUND_CARRIER(12 downto 4); when others => RF_OUT <= not AUDIO_SINE(15) & AUDIO_SINE(14 downto 6); end case;

i've got the multipliers ready to do modulation. The carriers are generated by a DDS core I found in the Xilinx tools. Did the DTO and sine table in a single core. Not always useful. The audio tone generator needs a 24 bit DTO to get frequency steps of just under 10Hz with a 148.5MHz clock. So I used a separate sine table which just takes the 12MSBs of the DTO. This is the highest resolution that uses just a single block RAM. Even then the core generator is doing 4 quadrant symmetry with some adders to achieve that. Not my problem, the core just does it

Now I need to sit down and do sums for the dynamic ranges of audio and video. Also need a temporary video generator running at 148.5MHz. I think I'll do a simple literal generator. That will be a 16kx8 or 16kx10 RAM. Even the smaller one will need 8x BRAM but that doesn't matter for experiments. The Xilinx I'm using has 84 of them. I'll bung a whole line of video, including sync pulses, into the RAM. Will need 14667 locations. (148.5MHz/10.125kHz) Will forget about field sync at this stage. It's only proof of principle.

I doubt I'll go beyond simple test pattern and tone. All I'm trying to do is prove the basic modulator ideas, not design a fully fledged system.