28-11-2018, 02:51 PM
(This post was last modified: 28-11-2018, 02:55 PM by ppppenguin.)
Follwoing your example I'm trying to bash together a rough and ready System A modulator here. The board I'm working on for a client has the following relevant resources:
148.5MHz clock
10 bit DAC
Spartan 3A series FPGA
The clock is just about fast enough to have a go at a Ch1 modulator.
A 10 bit DAC seems marginal but it's all I've got. It's also only spec'ed to just over 80MHz so I'm taking a flyer running it at 148.5MHz. It may work if I speak to it nicely. Clock to data timing may be a problem. I reckon to use an output normally specified for DDR memory to do accurately timed clock forwarding. It has worked well for other clock forwarding applications at 148.5MHz. The filter after the DAC is a simple 3 pole C-L-C design. I'd have to go back to my notes to check its frequency response or sweep it using the DAC. It may well be rolling off a bit by 45MHz. There's an opamp(LMH6714) after the filter to drive 75R video outputs but I doubt that will be the limiting factor as it's dead flat to well over 100MHz. The DAC etc was meant for very high accuracy PAL/NTSC and also trisync HD sync pulses. The DAC is normally clocked at 54MHz for PAL/NTSC and 74.25MHz for trisync.
http://www.ti.com/product/LMH6714
The FPGA has plenty of resources and 148.5MHz is no problem if I'm careful.
I'm also doing real development work for client on the board so I'm trying to parasite the modulator work on that. Provided it doesn't take too much time and effort. First pass is simply to get a carrier output. Though I probably should do a simple ramp first, just to see how the DAC works at 148.5MHz.
148.5MHz clock
10 bit DAC
Spartan 3A series FPGA
The clock is just about fast enough to have a go at a Ch1 modulator.
A 10 bit DAC seems marginal but it's all I've got. It's also only spec'ed to just over 80MHz so I'm taking a flyer running it at 148.5MHz. It may work if I speak to it nicely. Clock to data timing may be a problem. I reckon to use an output normally specified for DDR memory to do accurately timed clock forwarding. It has worked well for other clock forwarding applications at 148.5MHz. The filter after the DAC is a simple 3 pole C-L-C design. I'd have to go back to my notes to check its frequency response or sweep it using the DAC. It may well be rolling off a bit by 45MHz. There's an opamp(LMH6714) after the filter to drive 75R video outputs but I doubt that will be the limiting factor as it's dead flat to well over 100MHz. The DAC etc was meant for very high accuracy PAL/NTSC and also trisync HD sync pulses. The DAC is normally clocked at 54MHz for PAL/NTSC and 74.25MHz for trisync.
http://www.ti.com/product/LMH6714
The FPGA has plenty of resources and 148.5MHz is no problem if I'm careful.
I'm also doing real development work for client on the board so I'm trying to parasite the modulator work on that. Provided it doesn't take too much time and effort. First pass is simply to get a carrier output. Though I probably should do a simple ramp first, just to see how the DAC works at 148.5MHz.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
