FPGA System A modulator

[ppppenguin]

Another example of how to minimise logic delays, this time a range limiter.

if A > MAXVALUE then B <= MAXVALUE;
elsif A < MINVALUE then B <= MINVALUE;
else A < B;
end if;

Nice simple code but it's got to do 2 comparisons and some extra logic in 1 clock cycle.

So let's pipeline it. TOOHIGH and TOOLOW are boolean:

TOOHIGH <= (A>MAXVALUE);
TOOLOW <= (A< MINVALUE);
A1 <= A; -- Pipeline delay so that data matches TOOHIGH and TOOLOW
if TOOHIGH then A1 <= MAXVALUE
elsif TOOLOW then A! <= MINVALUE;
else B <= A1;
endif;

This separates the comparisons and the logic. I can't estimate the speed gain but it will matter at 180MHz. It won't matter at 60MHz.

I know what you mean about generating the SDC. In the older Xilinx ISE tools the UCF is easy enough to write by hand though there are tools available to help. In the newer VIvado tools the constraints such as pinout and timing are in XDC files. These have a more complex syntax than UCF so you tend to use the tools. In practice I've done the initial work using the tools, then edited by hand.

As projects get bigger it's useful to have multiple constraints files. At a minimum one for pinout and pin properties, another for timing.