FPGA System A modulator

[ppppenguin]

Remember that registers are essentially free in FPGAs. I've not yet done a design which used more registers than logic cells.

For example, if you're adding 3 signals, if you want high speed never write:

process (CK) begin
if rising_edge(CK) then
SUM <= A+B+C;
end if; --CK
end process;

This would cascade a pair of adders, introducing delay. Much better to write:

process (CK) begin
if rising_edge(CK) then
PARTSUM <= A+B;
DELAYED_C <= C;
SUM <= PARTSUM+DELAYED_C;
end if; --CK
end process;

There is an extra pipeline delay of 1 clock cycle but in most cases this doesn't matter.

At the 180MHz or so that you're working, it's absolutely essential to use timing constraints in the SDC file.