17-11-2018, 02:12 PM
Wow! What a brilliant result. The actual VHDL code for a modulator isn't very complex but actually doing it and getting such great looking results is a significant achievement.
The actual modulator code need be no more than:
MODULATED_OUTPUT <= UPSAMPLED_VIDEO * CARRIER;
This may not be fast enough as the inferred multiplier may need pipeline stages. Sometimes these can be inferred from the VHDL, otherwise you need to create a multiplier core and instantiate it. Frank already has experience of upsampling video by smaller factors in Hedghog so I would hope that the larger factor (x20) holds no terrors. The clock management in modern FPGAs makes generating the high clock frequency pretty easy. Might be easiest to start with the high frequency and divide down to pixel clock rather than the other way round.
Carrier generation is a DTO and sine table. Nothing too hard but it's got to run pretty fast. The raw carrier waveform will likely not be a very pure sine wave. Unless the LPF is perfect, even with a factor of about 3 between sample rate and output frequency there will be visible irregularities. I don't think this matters. If you want to investigate the subject in more detail scale frequencies down by a factor of 10 or whatever so you aren't pushing your scope too hard and possibly getting secondary effects.
What sort of output circuit have you got after the DAC? I would strongly recommend that you use both +ve and -ve outputs with a small transformer to do balanced to unbalanced. The transformer need be no more than a small ferrite "8" core or ring.
The actual modulator code need be no more than:
MODULATED_OUTPUT <= UPSAMPLED_VIDEO * CARRIER;
This may not be fast enough as the inferred multiplier may need pipeline stages. Sometimes these can be inferred from the VHDL, otherwise you need to create a multiplier core and instantiate it. Frank already has experience of upsampling video by smaller factors in Hedghog so I would hope that the larger factor (x20) holds no terrors. The clock management in modern FPGAs makes generating the high clock frequency pretty easy. Might be easiest to start with the high frequency and divide down to pixel clock rather than the other way round.
Carrier generation is a DTO and sine table. Nothing too hard but it's got to run pretty fast. The raw carrier waveform will likely not be a very pure sine wave. Unless the LPF is perfect, even with a factor of about 3 between sample rate and output frequency there will be visible irregularities. I don't think this matters. If you want to investigate the subject in more detail scale frequencies down by a factor of 10 or whatever so you aren't pushing your scope too hard and possibly getting secondary effects.
What sort of output circuit have you got after the DAC? I would strongly recommend that you use both +ve and -ve outputs with a small transformer to do balanced to unbalanced. The transformer need be no more than a small ferrite "8" core or ring.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
