New language....

[ppppenguin]

Concurrent vs sequential isn't an easy concept at first. The way I think about it is that if the logic is outside a process then it's just gates. If it's inside a process with a clock then it's a bunch of flipflops that all get clocked together. Here's a simple example from one of my designs with a clock enable. It's a 4 bit wide control register that's memory mapped at 070 hex. CWR is a write enable.

process (CKC) begin
if rising_edge(CKC) then
if (CONTROL_ADDRESS(11 downto 0) = X"070") and CWR = '1' then SET_WINDOW_START <= CONTROL_DATA(3 downto 0); end if;
end if; -- CKC
end process;

Intelligent use of boolean signals makes life easier. As does use of unsigned, signed and integer instead of SLV where sensible.

This function, in a "useful functions" file that's declared in all modules is a godsend:

-----------------------------------Boolean to standard logic----
Function to_std_logic(X: in Boolean) return std_logic is
variable ret : std_logic;
begin
if x then ret := '1'; else ret := '0'; end if;
return ret;
end to_std_logic;
--======================================

You can then write: my_standard_logic_signal <= to_std_logic(my_boolean_signal);

Another useful hint. When you've got an SLV that you need to assign to a constant it can get a bit tedious. Espeically when it's not a multiple of 4 bits long. This assigns a 27 bit SLV to 45(decimal) with minimum effort:
my_27_bit_slv <= conv_std_logic_vector(45,26));

The conversions between unsigned, signed, SLV and intgeger vary slightly according to which libraries you use. For historic reasons I still use:

use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;

This is old fashionedand strictly speaking proprietary to Synopsis but fully supported by everyone and always will be.

The modern way is to use:

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

If I changed my library declarations it would break a load of stuff in my designs and I'd get horribly confused. So I stick with the old ways. With the Vivado tools (it's a bit different on the old ISE tools) my library delcarations tend to read:

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library jb_lib;
use jb_lib.GENERAL_CONSTANTS.all; -- Constants that stay that way
use jb_lib.USEFUL_FUNCTIONS.all; -- Useful functions such as "to_std_logic" (boolean to std_logic)

Hope this helps a little.