23-05-2011, 12:34 PM
Typical problem in logic design in my own field of TV. Part of system at pixel clock rate, part at line rate. To be fully synch all the registers and counters in the parts that work at line rate need to have CE pulse once per line. This restricts the choice of registers and counters severely, unless you use the old trick of extra gating on registers to give a "hold" function.
Before PLDs and FPGAs skilled designers recognised the limitations of available parts and worked within them. I'm sure the PDP11 designers were in that category. Others just did the best they could which in some cases meant capacitors hung in odd places to suppress runt pulses.
If I want something as simple as (say) a 20 bit counter addressing a memory containing a literal TV image, clock rate around 13.5MHz, I have 2 plausible approaches. Either 5 off '161 counters or a PLD. The PLD programming is just a few lines of VHDL and can easily include reset when a top limit is reached. It's also nice and fast, so the delays won't eat into the timing budget too much. It's possible with '161 counters, if you get the carry lookahead right but they are still on the slow side unless you use one of the faster families.
I've never used PICs but understand that they execute instructions serially like most other CPUs. Not so useful if you want fast logic or stuff that's meant to run in parallel. I believe they are excellent for many applications and are easy to use and program, just that I haven't used them.
Before PLDs and FPGAs skilled designers recognised the limitations of available parts and worked within them. I'm sure the PDP11 designers were in that category. Others just did the best they could which in some cases meant capacitors hung in odd places to suppress runt pulses.
If I want something as simple as (say) a 20 bit counter addressing a memory containing a literal TV image, clock rate around 13.5MHz, I have 2 plausible approaches. Either 5 off '161 counters or a PLD. The PLD programming is just a few lines of VHDL and can easily include reset when a top limit is reached. It's also nice and fast, so the delays won't eat into the timing budget too much. It's possible with '161 counters, if you get the carry lookahead right but they are still on the slow side unless you use one of the faster families.
I've never used PICs but understand that they execute instructions serially like most other CPUs. Not so useful if you want fast logic or stuff that's meant to run in parallel. I believe they are excellent for many applications and are easy to use and program, just that I haven't used them.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
