01-02-2016, 05:31 PM
First pass of controller schematic.
U1 (4060) is an oscillator and divider. Q2 and Q3 sequence round the 4 switch banks via U2 (4051) which applies 0V to the common point of the relevant bank. U6-U9 (74LS30) encode up to 16 switches to 4 bit binary as needed by the router.
When the system is in standby mode U2 is disabled and either U3 (for off air) or U4 (for testcard) is enabled. These force the selection on each bank. No point in forcing the preview bank as the monitoring system is switched off in standby.
U5 (74HCT138) also decodes Q2 and Q3 to pulse the latch enables in the router. Using Q0 and Q1 to enable the decoder ensure that the latch enables are only pulsed when the data is stable.
I think I have chosen the arrangment of Q0 and Q1 so that no glitches occur on the '138 outputs, even though the counter outputs are not synchronous. Actually even if U1 was a synchronous counter you should never rely on the outputs being exactly cotimed. Get the design wrong and you can still get glitches, nasty very short ones that give horrible intermittent problems. This is not the time or place for a tutorial on synchronous logic design but I'm sure there's plenty of guidance online.
U1 (4060) is an oscillator and divider. Q2 and Q3 sequence round the 4 switch banks via U2 (4051) which applies 0V to the common point of the relevant bank. U6-U9 (74LS30) encode up to 16 switches to 4 bit binary as needed by the router.
When the system is in standby mode U2 is disabled and either U3 (for off air) or U4 (for testcard) is enabled. These force the selection on each bank. No point in forcing the preview bank as the monitoring system is switched off in standby.
U5 (74HCT138) also decodes Q2 and Q3 to pulse the latch enables in the router. Using Q0 and Q1 to enable the decoder ensure that the latch enables are only pulsed when the data is stable.
I think I have chosen the arrangment of Q0 and Q1 so that no glitches occur on the '138 outputs, even though the counter outputs are not synchronous. Actually even if U1 was a synchronous counter you should never rely on the outputs being exactly cotimed. Get the design wrong and you can still get glitches, nasty very short ones that give horrible intermittent problems. This is not the time or place for a tutorial on synchronous logic design but I'm sure there's plenty of guidance online.
www.borinsky.co.uk Jeffrey Borinsky www.becg.tv
